Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

Abstract: An organic electroluminescence device that includes, between an anode 41 and a cathode 42, an organic layer stacked structure 43 that comprises stacked plural emitting layers that emit light of different colors, wherein the organic electroluminescent device comprises, between the emitting layers, at least one intermediate layer that comprises a compound represented by the following formula (1) in which at least one of Ar1, Ar2 and Ar3 is a group represented by the following formula (2):

Abstract: An organic electro-luminescence display device includes a first substrate, plural pedestals which are provided in a convex shape on the first substrate and have inclined side surfaces, plural first electrodes respectively provided on the respective side surfaces of the pedestals, an organic electro-luminescence film which is provided above the plural pedestals and includes a light-emitting layer laminated on the plural first electrodes, and a second electrode which is provided above the plural pedestals and is laminated on the organic electro-luminescence film. Light generated in the light-emitting layer is transmitted between a first reflection surface and a second reflection surface. The second electrode includes light transmission parts, through which the light passes, above upper end parts of the pedestals. A surface of the second electrode facing the organic electro-luminescence film is the second reflection surface except for the light transmission parts.

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract: An organic light-emitting device including a first electrode; a second electrode; and an organic layer, the organic layer including an emission layer, a hole transport region including a hole transport layer, a hole injection layer, or a buffer layer, and an electron transport region including a hole blocking layer, an electron transport layer, or an electron injection layer, wherein a triplet energy of a hole transport material of the hole transport layer is from about 2.4 to about 3.2 eV, an electron affinity of the hole transport material is from about 2.2 to about 2.6 eV; the triplet energy of the hole transport material is greater than a triplet energy of a dopant of the emission layer and a triplet energy of a host material of the emission layer, the host material of the emission layer includes the compound represented by Formula 1.

Abstract: The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor.

Abstract: Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is attached to the first semiconductor die. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die. Methods of forming semiconductor devices may involve attaching a second semiconductor die to a first semiconductor die. The first semiconductor die includes a heat-generating region at a periphery thereof. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die.

Abstract: A method for making a LED comprises following steps. A substrate having a first surface and a second surface is provided. A patterned mask layer is applied on a first surface. A number of three-dimensional nano-structures are formed on the first surface and the patterned mask layer is removed. A first semiconductor layer, an active layer and a second semiconductor layer are formed on the second surface. A first electrode and a second electrode are formed to electrically connect with the first semiconductor layer and the second semiconductor pre-layer respectively.

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract: Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract: A double seal ring for an integrated circuit, the double seal ring includes a first seal ring surrounding the integrated circuit and a second seal ring spaced from the first seal ring. The double seal ring further includes two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop. A method of forming a double seal ring for an integrated circuit includes forming a first seal ring surrounding the integrated circuit and forming a second seal ring spaced from the first seal ring. The method further includes forming two connectors connecting the first seal ring and the second seal ring, wherein the first seal ring, the second seal ring, and the two connectors form a closed loop.

Abstract: The present invention relates to optoelectronic device layer structures, light emitting devices, and detectors based upon heterostructures formed between hexagonal boron nitride (hNB) and III nitrides, and more particularly, to heterojunction devices capable of emitting and detecting photons in the ultraviolet (UV) and extremely ultraviolet (RUV) spectral range. The present invention also relates to neutron detectors based on epitaxially grown hBN thin films (or epitaxial layers) and hBN stacked thin films (or epitaxial layers) to satisfy the thickness required for capturing all incoming neutrons.

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

Abstract: A device includes a semiconductor substrate, and a capacitive sensor having a back-plate, wherein the back-plate forms a first capacitor plate of the capacitive sensor. The back-plate is a portion of the semiconductor substrate. A conductive membrane is spaced apart from the semiconductor substrate by an air-gap. A capacitance of the capacitive sensor is configured to change in response to a movement of the polysilicon membrane.

Abstract: A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.

Abstract: According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)?Wi)/Wi?0.008.