Abstract: An analog to digital converter as implemented by large scale integrated circuit techniques utilizing charge coupled device technology. On a single integrated circuit chip, the necessary gate and charge packet transfer paths are formed to allow for the analog to digital conversion. Depending on the amount of charge transferred from one location to the next the two outputs will denote a digital voltage level indicative of logic 0 or logic 1.
Abstract: The electronic measuring system includes a novel power supply which converts D.C. from a D.C. source to voltage pulses to drive a transducer. During intervals between transducer power pulses, an automatic drift compensation system stores an indication of system drift for use during a subsequent power pulse period. The system includes stability sensing means which render the system inoperative for measurement purposes when the signal from the measuring transducer is unstable. A plurality of sample measurement signals are taken and stored, and then passed through a programmable low pulse filter to accomplish a measurement. Thus each measurement is the result of a plurality of measurement cycles.
Abstract: Received periodic pulses of varying amplitude, representing a measured analog signal, are alternately applied to two interpolation channels through gates alternately activated by a flip-flop element responsive to each incoming pulse. Each channel converts the applied pulses into an interpolated value which is summed with that of the other channel to substantially reproduce the original analog signal value. In a first specific arrangement, each pulse is converted, by the integration of the stored pulse amplitude, into a triangular shaped signal having a height equal to the corresponding pulse amplitude and a base equal to twice the pulse spacing. The successive triangular signals from each channel, each overlapping the adjacent pulse signals from the other channel, are summed to produce an interpolated analog output substantially equivalent to the original analog signal.
Abstract: A shaft, the angular position of which is to be detected, equipped with a notched disk one tooth of which has been removed. A position sensor detects the passage of the teeth for a Schmitt trigger with its output connected to the inputs of two monostable multivibrators, to the up-down counter input of a counter, to one input of an AND gate and to the inputs of logic circuits. The held output of the counter is connected to an input of a type D flip-flop connected at its output to the second input of the AND gate.
Abstract: A digital-to-analog converter of a pulse width modulation type in which a single counting cycle of a clock pulse counter is divided into 2.sup.m elementary periods where m represents a selected number of less significant bits of a digital input data to be converted into analog quantity and elementary pulses in number determined in dependence on the logic values of the more significant bits are distributed among the elementary periods, while supplementary elementary pulses are produced in the elementary periods selected in dependence on the logic values of the less significant bits of the digital input data. These elementary pulses are integrated for every elementary period and the integrated output value is converted into a corresponding DC analog output signal.
Abstract: The video speed logarithmic analog-to-digital converter includes a plurality of parallel paths. In a first path, a plurality of comparators compare an analog input signal with a plurality of logarithmically incremented first reference signals. The number of first reference signals which fail to exceed the analog input signal is converted into a binary representation of the most significant bits of the logarithm of the analog input signal. A second parallel path determines the least significant bits by producing a logarithmically attenuated analog input signal and comparing the attenuated analog input signal with a plurality of logarithmically incremented second reference signals. The number of second reference signals which fail to exceed the attenuated analog input signal is converted into a binary representation of the least significant bits of the logarithm of the analog input signal.
Abstract: An interpolative PCM decoder converts PCM signals having polarity bits, segment selection bits and uniform quantization bits into an analog signal. The PCM decoder may be used both for .mu.-law and A-law conversion by use of simple circuits and includes an AND gate circuit which produces a logical product between a selection signal for selecting a minimum unit of an analog value of a lower end of a segment and a control signal for change-over between the .mu.-law and the A-law, and a circuit generating the same analog values as the minimum unit of the analog value in accordance with an output of the AND gate circuit.
Abstract: A quantizer network is disclosed for decoding an analog signal and providing a four-bit digital output. The analog input signal is divided or quantized into sixteen discrete voltage ranges and applied to sixteen differential amplifiers. Each amplifier has a different reference which must be exceeded before it provides an output signal. The sixteen differential amplifiers are connected to nine latch networks which respond to the signals from the amplifiers and provide a cyclic code in response thereto. The latch networks are connected to a network of logic gates which decode the cycle code into a four-bit digital output signal. The output signals from the logic gate network are applied to output stages which extend the valid time of the output signal from the logic gates.
Abstract: A method and an apparatus are disclosed for converting an analog input signal having either a positive or negative polarity into a digital output signal indicating the magnitude and polarity of the input signal. Amplifier offset voltages and dynamic hysteresis in the comparator are compensated automatically and a zero reference is established automatically to provide a corrected output. A compensation capacitor and an integrating capacitor are selectively charged. A reference signal is integrated to measure the magnitude of the difference between the integrator offset voltage and the comparator threshold. A digital representation of the time required to measure the difference between the integrator offset voltage and the comparator threshold is stored. The compensation capacitor and the integrating capacitor are again selectively charged. The analog input signal is then integrated for a fixed time. The reference signal is integrated for a time equivalent to the digitally stored time.
Abstract: A system for performing real time quantization and analog/digital conversion of an analog waveform operating with analog input signals over one gigahertz bandwidth is realized by utilizing a CRT type device in which the electron beam is deflected by the analog input waveform. The deflected electron beam strikes a fast phosphor screen and an externally positioned target consisting of light sensitive elements arranged in a discrete pattern detects and quantizes the signal. The output of the detectors feed an encoder resulting in a binary digital output waveform. The device accepts both unipolar and bipolar video waveform and has parallel output channels such that further circuitry to be employed can operate with reduced bandwidths.
March 30, 1979
Date of Patent:
October 7, 1980
The United States of America as represented by the Secretary of the Air Force
Abstract: A novel analog-to-digital converter is integrated on a semiconductor substrate utilizing I.sup.2 L techniques. The resulting converter, which utilizes dual slope integration to generate a digital signal, operates from a single low-voltage power supply and has few external components. The converter is suitable for integration with I.sup.2 L digital circuitry to provide a complete digital system, which operates in accordance with an analog input signal, on a single semiconductor chip.
Abstract: The surface elastic wave device is an integral part of an analog-digital converter with intermediate frequency conversion. It is comprised of the acoustical part of a 4-pole surface elastic wave oscillator, a surface elastic wave reflector with track shifting working as a filter assembly and comprising one supply track and several return tracks having different angular frequencies, the reflector operating as a plurality of filters, and output transducers overlapping the return tracks and connected to detectors producing the digital information. Many types of reflectors and output transducer assemblies are described. The invention is useful with analog-digital converters having medium access times.
October 3, 1978
Date of Patent:
September 30, 1980
Michel Feldmann, Jeannine Le Goff epouse Henaff
Abstract: The combination of integrated injection logic (I.sup.2 L) and linear circuitry permits fabrication of a highly dense analog-to-binary coded decimal (A-to-BCD) converter. The heart of the A-to-BCD converter is a linear-I.sup.2 L plurality of high density variable current sinks which are proportional to each other in combination with I.sup.2 L gating techniques. These variable current sinks, when used in combination with the I.sup.2 L constant current sources, current sensing means, and I.sup.2 L logic, provide a highly dense A-to-BCD converter.
Abstract: A digital optical display device incorporated in a scale including a movable measuring member, a code plate with opaque and transparent areas, a stationary light source irradiating the code plate, a seven-segment display adjacent the code plate and having light guide inlets receiving the coded light transmitted through the code pattern on the code plate, a magnetic indexing system associated with the code plate and defining a multiplicity of magnetic indexing locking positions arranged in step by step relation to each other to retain the code plate in any of the multiplicity of discrete positions; a spring coupling between the measuring member and the code plate and yieldable within one magnetic index position of the location at which the measuring member has stopped to locate the code plate at the position of a discrete code pattern.
Abstract: Delta modulation decoder comprising an integrating network provided with a first integrating capacitor which is on the one hand connected to an input terminal of the integrating network and on the other hand to ground potential through a second integrating capacitor. The 1-pulses and the 0-pulses of the delta modulation signal, applied to the decoder, are applied to a current source circuit generating a positive charging quantum in response to each 1-pulse and a negative charging quantum in response to each 0-pulse. Said charging quanta are applied to the input terminal of the integrating network through a correction network. This correction network is controlled by the voltage V.sub.C3 across the second integrating capacitor, so that, if V.sub.C3 is positive, the positive charging quanta are reduced and/or the negative charging quanta increased and that, if V.sub.C3 is negative, the positive charging quanta are increased and/or the negative charging quanta reduced.
Abstract: A franking machine having a locating operation applied to one out of ten tinct positions of value setting components, with five transducers provided for delivery of 5-bit coded activation information zones which makes it possible to check the accuracy of the information collected by the transducer.
June 6, 1977
Date of Patent:
September 23, 1980
Societe d'Etude et de Construction d'Appareils de Precision (S.E.C.A.P.)
Abstract: Data acquired from a source such as a coded disc is processed so as to be free of ambiguities associated with boundary transitions where the data source produces groups of bits which have least significant ordering and higher significant ordering. Wherever a common transition boundary between the bit groups occurs, ambiguities from misalignment of these boundaries are avoided by controlling the higher ordered bit transitions from the lower ordered bit transitions. Circuitry tracks and stores the higher order bits by synchronous updating whenever no misalignment or skew sensitive transitions are encountered. Logic circuitry continuously inspects the lower significant bits to determine the presence or absence of a zone surrounding the common transition boundary and also detects the actual passage and direction of the transition boundary in the lower significant bit group. This logic corrects the counter stored higher order bit counts in conformity with the status of the lower significant bit states.
Abstract: Apparatus and method for converting an analog input signal to a digital signal by modulating the analog signal with a periodic triangular wave-shape signal to produce intermediate digital signals and Exclusive-ORing these intermediate signals with a square wave signal having the same phase as the triangular wave-shape signal.
Abstract: An analog-to-digital converter includes a first and a second comparator. The first comparator generates a plurality of quantizing outputs defining voltage gaps and also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose shifted reference output voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps.
June 17, 1977
Date of Patent:
August 19, 1980
Pern Shaw, Fuad H. Musa, Stephen J. Kreinick