Abstract: An example system includes an enclosure having a plurality of small computer system interface (SCSI) drives partitioned into a first zone including a first SCSI drive of the plurality of SCSI drives and a second zone including a second SCSI drive of the plurality of SCSI drives. The system includes a plurality of communication ports having a first port through which the first zone communicates; and a second port through which the second zone communicates. The system includes a management node configured to interact with the first SCSI drive in a first server as a first Internet SCSI (iSCSI) drive, and with the second SCSI drive in a second server as a second iSCSI drive.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: Described herein are nodes, sub-systems and systems of nodes for use in a dynamic node based computer. In some embodiments, nodes include: one or more signal receivers for detecting or receiving one or more input signals from one or more signal sources, one or more signal transmitters for selectively connecting and transmitting signals to one or more other nodes; and a threshold device configured to control the selective operation of the signal transmitter based on a threshold derived from one or more characteristics of the input signals. More complex variations of the nodes include the addition of threshold manipulation devices, signal amplifiers or dampeners, control devices, or computational devices. Also described herein are machines or devices built from one or more such nodes.

Abstract: A system and method for full body movement control of dual joystick operated devices. The system uses two motion sensors: a first motion sensor for body lean and tilt, and a second motion sensor for head rotation and tilt. The output from the first motion sensor is converted into a virtual joystick output signal corresponding to a first standard joystick which controls one aspect of movement, and the output from the second motion sensor is converted into a virtual joystick output signal corresponding to a second standard joystick which controls a different aspect of movement.

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Abstract: A data processing apparatus includes a power-source controller, a data processing device, a physical-layer section, a communication controller, and a state controller. The power-source controller controls a first power-source setting and a second power-source setting. The second power-source setting causes less electric power consumption than the first power-source setting. The communication controller performs the communication with the data processing device through a predetermined communication path and the physical-layer section under the first power-source setting. The communication controller stops the communication with the data processing device through the communication path and the physical-layer section under the second power-source setting. The state controller maintains the second communication state with respect to the data processing device side of the communication path while electric power supply to the physical-layer section is reduced under the second power-source setting.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: An information handling system may include a basic input/output system (BIOS), a management controller configured to provide out-of-band management of the information handling system, a plurality of communications bus root complex ports, and a storage backplane having a plurality of slots configured to receive respective storage resources. The information handling system may be configured to: store, at the management controller, an initial data structure containing a correspondence between the plurality of communications bus root complex ports and the plurality of slots; transmit, from the BIOS to the management controller, information regarding bus numbers for a plurality of enumerated information handling resources coupled to the communications bus; and determine, by the management controller, a correspondence between the bus numbers and the plurality of slots.

Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.

Abstract: A semiconductor device of a peripheral device control system includes one or more management blocks that are provided in association with a device to be controlled. The management blocks each include a plurality of registers that store information pertaining to each operation of the device to be controlled, and a first generation unit that performs a predetermined aggregation process on values of the plurality of registers included in the management block to generate an aggregation value that is a value formed by aggregating the values of the plurality of registers.

Abstract: A method for performing detection control of a write protection function of a memory device, an associated control chip, and an associated electronic device are provided. The method includes: detecting whether the memory device supports a first protocol to generate an interface detection result; detecting whether a write protection switch of the memory device is turned on to generate a write protection detection result; and according to the interface detection result and the write protection detection result, selectively initializing a transmission interface of a control chip as a first transmission interface conforming to the first protocol or a second transmission interface, to allow a host device to access the memory device through the control chip, wherein the first transmission interface corresponds to a first configuration of the control chip, and the second transmission interface corresponds to a second configuration of the control chip.

Abstract: Provided is a terminal for controlling an external device, not equipped with its own memory or controller, connected to the terminal. The portable terminal, when being connected to at least one external device, changes its setting with an extracted setting data matching the connected external device. Accordingly, the connected external device in a connection state to the portable terminal performs corresponding operations under control of the portable terminal.

Abstract: An extension of the existing CAN FD data transmission protocol. The extension enables the use of the IPv6 protocol for the CAN bus. The CAN FD protocol is further developed in an incompatible way. One modification measure relates to the lengthening of the Data Field, which is positioned in the transmission frame after an Arbitration Field. An arbitrary number of bytes can be entered in the extended Data Field within a specified upper limit. Since the Data Field is transmitted at a higher bit rate field than the Arbitration Field, the data throughput is increased dramatically.

Abstract: Systems and methods are disclosed to perform a function level reset in a memory controller, in accordance with certain embodiments of the present disclosure. In some embodiments, an apparatus may comprise a storage controller circuit configured to receive a function reset indicator from a host device, the function reset indicator identifying a selected storage controller function executing at a storage controller of the apparatus. The circuit may abort each command associated with the selected function and pending at the apparatus based on the function reset indicator, verify that no commands associated with the selected function remain pending at the apparatus, and clear registers associated with the selected function based on the determination that no commands associated with the selected function remain.

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A dual-integrated gate-driver with reverse current protection (RCP) fault protection is described. A Universal Serial Bus Type-C (USB-C) controller includes a first terminal, a second terminal, and a dual-gate driver. The dual-gate driver drives a first power field effect transistor (FET) coupled to the first terminal and a second power FET coupled to the second terminal. The first power FET and the second power FET are connected in series between a voltage bus (VBUS_C) terminal of a USB Type-C connector and a voltage supply to deliver power to the VBUS_C terminal. A breakdown voltage of each of the first power FET and the second power FET is less than 20 volts. The dual-gate driver controls the first power FET and the second power FET in response to at least one of a short circuit event or a reverse current event.

Abstract: A flexible standards-based bridge or switch chiplet facilitates heterogeneous integration of chiplets that support different physical layer (PHY) interfaces and communication protocols. The bridge chiplet is configured with multiple PHY interfaces and associated adapter logic and translation logic for translation between different PHY interfaces and protocols. The bridge chiplet can be programmed to serve as a die-to-die interconnect bridge that routes data between multiple chiplets supporting different PHYs and interconnect protocols. Some embodiments of the bridge chiplet can serve solely as a PHY bridge, while others may serve as a bridge for both PHYs and protocols.

Abstract: Aspects of the present disclosure relate to internet of things (IoT) device management. A first set of sensor data can be received from a first IoT device within an IoT sensor network, the IoT sensor network containing a plurality of IoT devices, wherein a subset of the plurality of IoT devices within the IoT sensor network are in an inactive state. The first set of sensor data can be analyzed to determine whether an activation condition is satisfied. In response to determining that the activation condition is satisfied, a second IoT device within the subset can be activated, wherein activation leads to collection of a second set of sensor data from the second IoT device.