Abstract: Aspects of the present disclosure relate to internet of things (IoT) device management. A first set of sensor data can be received from a first IoT device within an IoT sensor network, the IoT sensor network containing a plurality of IoT devices, wherein a subset of the plurality of IoT devices within the IoT sensor network are in an inactive state. The first set of sensor data can be analyzed to determine whether an activation condition is satisfied. In response to determining that the activation condition is satisfied, a second IoT device within the subset can be activated, wherein activation leads to collection of a second set of sensor data from the second IoT device.

Abstract: A device can include a server that includes a host processor and at least one hardware acceleration (hwa) module having at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

Abstract: A port adaptation method applied to a network device including a port adaptation apparatus includes probing whether the first port and the second port are connected to power sourcing equipment, and maintaining or changing one of the first port and the second port that is connected to power sourcing equipment as, or to, a powered state, and a state of the other port as, or to, a powering state.

Abstract: Systems and methods are disclosed for efficient management of bus bandwidth among multiple drivers. An example method may comprise: receiving a request from a driver to map the driver to a device memory of a device to allow the driver to write data on the device memory via a bus; mapping the driver to a random access memory (RAM) such that the driver is to write the data to the RAM; reading contents of the RAM at a specified interval of time to determine whether the data written by the driver is accumulated in the RAM; responsive to determining that the data written by the driver is accumulated in the RAM, determining whether a bandwidth of the bus satisfies a bandwidth condition; and responsive to determining that the bandwidth satisfies the bandwidth condition, forwarding, via the bus, a portion of the data written by the driver in the RAM to the device memory.

Abstract: An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port are to be respectively coupled to a first device with a first class type, a second device with a second class type, and a third device with a third class type. The controller is to determine that individual ones of the first and second devices are to perform asynchronous transfer with the apparatus, and that the third device is to perform a transfer that is different from the asynchronous transfer. The controller is to allocate bandwidth to the first and second I/O ports, based at least in part on the first class type and the second class type. The controller is to ignore the third class type, while allocating bandwidth to the third I/O port.

Abstract: An oscillation reduction unit for a bus system. The oscillation reduction unit has two transistors, which are situated anti-serially between a first bus wire of a bus of the bus system and a second bus wire of the bus, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and a time control block for switching the two transistors and designed to switch on the two transistors while a signal on the first and/or second bus wire and/or a transmission signal, from which the signals on the first and/or second bus wire are generated, changes from a dominant state to a recessive state, and designed to switch off the two transistors if the signal on the first and/or second bus wire and/or the transmission signal is/are switched into the recessive state.

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.

Abstract: A method for bandwidth allocation includes receiving requests for bus channel access from two or more master devices. Next, the method selects one of priority-based allocation or credit-based allocation. Upon selecting the priority-based allocation, the method grants bus channel access based on pre-assigned priorities for bus channel access. Upon selecting credit-based allocation, the method grants bus channel access based on pre-allocated credits for bus channel access, and the method decrements the credit from the master device that has been granted bus channel access.

Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array.

Abstract: A bus driver for driving a differential data bus can be in a dominant data bus state and in a recessive data bus state. In the dominant data bus state, the bus driver connects the first and second single-wire data bus lines to a first and second electrical potential and temporarily does not drive the first and second single-wire data bus lines in the recessive data bus state. In the recessive data bus state after a change from the dominant data bus state to the recessive data bus state, bus driver connects the first and second single-wire data bus lines to a fourth electrical potential for an active time.

Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

Abstract: A communication controller, a method and a node agent is disclosed, The communication controller comprising: a data transmission port configured to be connected to corresponding logical channels; an application port configured to provide data to or from corresponding applications; a node agent having node control data comprising at least one trained machine learning model, configured to: monitor performance characteristics for data inflow to a data transmission port; monitor an at least one local observable; control the connection between the data transmission port and another data transmission port causing outflow of data, or between the data transmission port and the application port, causing inflow of data if the application port receives data, and outflow of data if the application port sends data; control the connection between the transmission ports and the application ports based on the monitored performance characteristics, the at least one local observable, the at least one trained machine learning m

Abstract: A system for camera device discovery and enumeration detects a camera device connected to a computing device using a Universal Plug and Play (UPnP) protocol and generates a device object corresponding to the detected camera device with a user-mode camera driver. The user-mode camera driver associated with an operating system executing on the computing device. The system registers the generated device object with the operating system to provide a direct interface from the operating system to the camera device and to make the camera device available to a plurality of applications executing on the computing device and commands the camera device from at least one of the plurality of applications via the registered device object through the operating system, thereby improving the functioning of the computing device and the user experience.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

Abstract: A system having information equipment connected in a daisy chain, where power supply control of the daisy chain-connected information equipment is performed without having to add a dedicated power supply control device. In a daisy chain connection system, second information equipment comprise a control unit and a power supply unit, and a first information equipment and the control unit of the second information equipment include a communication circuit capable of wired communication, and the first information equipment and the power supply unit of the second information equipment include a wireless circuit capable of wireless communication. When turning OFF a power supply to any one of the second information equipment, the first information equipment requests the power supply unit to stop the power supply by using wireless communication, and the power supply unit performs control for stopping the power supply to the control unit according to the request.

Abstract: A network adaptor (or NIC) is equipped with multi-level protocol processing capability and is implemented with a protocol processing pipeline that has multiple tap points to enable the integration of co-processors to operate with the NIC. The capability leverages the protocol processing pipeline and all the existing NIC software while at the same time enabling the integration of value added co-processors to customize and enhance the NIC capabilities.

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node and a second computer node. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; and (B) transmitting, by the first BMC and to the second BMC via electrical connection between the first and second BMCs, a reset signal that corresponds to the reset command, so as to trigger reset of the second BMC.