Abstract: Systems and devices are provided for fully discharging leakage current generated during standby and/or power down modes regardless of variations in PVT conditions. An apparatus may include a power generation unit that powers components of the apparatus and a bleeder circuit. The bleeder circuit may include an operational amplifier. Further, the bleeder circuit may include leakage current generator circuitry that is coupled to the operational amplifier and generates a first current that mimics leakage current generated by the power generation unit. Furthermore, the bleeder circuit may include leakage current mirroring circuitry that is coupled to an output of the operational amplifier and that generates a second current that mirrors the first current. In addition, the bleeder circuit may also include leakage current bleeder circuitry that is coupled to the leakage current mirroring circuitry and that generates a third current that sinks the leakage current to ground.

Abstract: Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.

Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

Abstract: A data sensing device and a data sensing method are provided. The data sensing device includes a current adjuster and a sensing amplifier. The current adjuster corresponds to a memory string of a memory array, generates a shift current according to an amount of a plurality of input signals of the memory string, and generates an adjusted read-out current by adjusting a read-out current of the memory string according to the shift current. The sensing amplifier receives the adjusted read-out current and a plurality of reference currents, and generates a read-out data by comparing the adjusted read-out current and the plurality of reference currents.

Abstract: A computer-implemented method for efficient assembly of oligonucleotides for nucleic acid based data storage includes receiving encoded data including binary data encoded into nucleic acid sequence data, and assembling a target nucleic acid data strand based on the encoded data by, concatenating one or more selected codeword oligonucleotides obtained from a codeword stack strand.

Abstract: A spin current magnetization rotational element including a first ferromagnetic metal layer in which a magnetization direction is variable, and a spin-orbit torque wiring that extends in a second direction intersecting a first direction that is a plane-orthogonal direction of the first ferromagnetic metal layer, and is joined to the first ferromagnetic metal layer. The first ferromagnetic metal layer has a lamination structure including a plurality of ferromagnetic constituent layers and a plurality of nonmagnetic constituent layers which are respectively interposed between the ferromagnetic constituent layers adjacent to each other.

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.

Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host performance boost mode of operation to ameliorate erroneous or potentially malicious access to the memory device, and efficiently providing refreshed mapping information to the host during the host performance boost mode of operation.

Abstract: A three-terminal device is disclosed having a magnetic tunnel junction (MTJ) and a spin orbit torque (SOT) generating layer. The MTJ has a first magnetic layer, a tunnel barrier layer underlying the first magnetic layer, and a second magnetic layer underlying the tunnel barrier, wherein the SOT generating layer is directly underlying the second magnetic layer. The second magnetic layer has a shape that is non-symmetrical, such that an average magnetization of a remnant state associated with the second magnetic layer has an in-plane component that is orthogonal to a current direction in the SOT generating layer.

Abstract: A memory device includes a memory array, a sensing circuit, a delay circuit and a controller. The memory array includes a plurality of blocks. The sensing circuit reads data of a selected block of the memory array according to a sensing signal and outputs corresponding output data according to a latch signal. The delay circuit outputs the latch signal. After the sensing signal is enabled, the controller controls the delay circuit to count, to delay output of the latch signal accordingly.

Abstract: A material may include at least one of BixSe(1-x), BixTe(1-x), or SbxTe(1-x), where x is greater than 0 and less than 1. In some examples, the material exhibits a Spin Hall Angle of greater than 3.5 at room temperature. The disclosure also describes examples of devices that include a spin-orbit torque generating layer, in which the spin-orbit torque generating layer includes at least one of BixSe(1-x), BixTe(1-x), or SbxTe(1-x), where x is greater than 0 and less than 1. In some examples, the spin-orbit torque generating layer exhibits a Spin Hall Angle of greater than 3.5 at room temperature.

Abstract: A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory, and a controller that stores an on-cell count in the buffer memory, the on-cell count indicating a number of memory cells, which are turned on by a read level applied to a reference word line of each of the plurality of blocks, from among memory cells connected to the reference word line.

Abstract: A nonvolatile memory device includes a memory cell array includes memory cells, a row decoder, a page buffer circuit and a control logic circuit. The row decoder is connected to the memory cells through word lines and includes switches configured to select the word lines, respectively. The page buffer circuit is connected to the memory cell array through bit lines. The control logic circuit is configured to perform operational functions when the row decoder turns on a switch corresponding to a particular word line among the word lines.

Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

Abstract: A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.