Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate, a first signal line formed over the substrate and a first insulating layer formed over the substrate and the first signal line. The display device also includes a second signal line formed over the first insulating layer and including an overlapping area that overlaps the first signal line, a second insulating layer formed over the second signal line and having a via hole that exposes at least a part of the overlapping area. The display device further includes an auxiliary wiring layer covering the via hole and connected to the overlapping area through the via hole.

Abstract: An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface.

Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.

Abstract: A photo-sensing unit including a first electrode, a first insulation layer, a photo-sensing structure and a second electrode is provided. The first insulation layer covers the first electrode and has an opening exposing the first electrode. The photo-sensing structure is located on the first electrode and disposed in the opening of the first insulation layer. The photo-sensing structure includes a first photo-sensing layer and a second photo-sensing layer stacked with each other. A material of the first photo-sensing layer is SixGeyOz. A material of the second photo-sensing layer is SivOw. The second electrode covers the photo-sensing structure. A photo-sensing apparatus including the photo-sensing unit and a fabricating method of a photo-sensing unit are also provided.

Abstract: According to various embodiments, a semiconductor structure may include: a first source/drain region and a second source/drain region; a body region disposed between the first source/drain region and the second source/drain region, the body region including a core region and at least one edge region at least partially surrounding the core region; a dielectric region next to the body region and configured to limit a current flow through the body region in a width direction of the body region, wherein the at least one edge region is arranged between the core region and the dielectric region; and a gate structure configured to control the body region; wherein the gate structure is configured to provide a first threshold voltage for the core region of the body region and a second threshold voltage for the at least one edge region of the body region, wherein the first threshold voltage is less than or equal to the second threshold voltage.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.

Abstract: A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

Abstract: An integrated circuit memory comprises an intermediate layer disposed between a plurality of bit lines in a bit line conductor layer and a plurality of word lines in a word line conductor layer. The intermediate layer includes a plurality of memory posts through an interlayer insulating structure. Each memory post has a memory element and an access element. The interlayer insulating structure includes higher thermal resistance at the level of the memory element than at the level of the access element.

Abstract: A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode.

Abstract: An integrated circuit includes a first semiconductor device, a second semiconductor device, and a metal shielding layer. The first semiconductor device includes a first substrate and a first multi-layer structure, and the first substrate supports the first multi-layer structure. The second semiconductor device includes a second substrate and a second multi-layer structure, and the second substrate supports the second multi-layer structure. The metal shielding layer is disposed between the first multi-layer structure and the second multi-layer structure, wherein the metal shielding layer is electrically connected to the second semiconductor device.

Abstract: A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode layer; source lines formed over an uppermost one of the conductive layers; first slits passing through the pipe gate electrode layer at positions overlapping with the source lines, and dividing the pipe gate electrode layer into a plurality of pipe gate electrodes, and second slits passing through the conductive layers at positions different from the first slits, and dividing the conductive layers into a plurality of memory blocks.

Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.

Abstract: A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.

Abstract: A radio frequency (RF) module comprises RF-shielding structure for providing three-dimensional electromagnetic interference shielding with respect to one or more RF devices disposed on the module. The RF-shielding may comprise wirebond structures disposed adjacent to or surrounding an RF device. Two or more intramodule devices may have wirebond structures configured to at least partially block certain types of RF signals disposed between the devices, thereby reducing effects of cross-talk between the devices.

Abstract: This disclosure provides an array substrate and manufacturing method thereof, as well as a display device, the array substrate comprising: a substrate and a pattern comprising a source and a drain located on the substrate, further comprising: a tunnel junction structure located between the substrate and the pattern comprising the source and the drain, the tunnel junction structure forming an active layer of the array substrate and resulting in tunneling effect. The above array substrate and the manufacturing method thereof, as well as the display device have one or more beneficial effects as follows: a relatively high current carrier mobility, a higher switching speed of TFT; the threshold voltage of the TFT is not easily drifted, and has a relatively high uniformity; each pixel can use less TFTs, the switching speed of the pixel is higher; and the fabricating process is simpler and more practicable.

Abstract: An optoelectronic device is provided. The optoelectronic device comprises: an optoelectronic system for emitting light; multiple contact regions on the optoelectronic system and separated from one another; and multiple fingers on the optoelectronic system and opposite to the multiple contact regions; wherein a first contact region in the multiple contact regions is between two adjacent fingers, and a first distance between the first contact region and one of the adjacent fingers is between 5% and 50% of a second distance between the two adjacent fingers.

Abstract: An integrated circuit packaging structure comprises at least one Micro Electrical Mechanical Systems (MEMS) gyroscope die mounted directly on a multi-layer flexible substrate having at least one metal layer and wire-bonded to the flexible substrate and a lid or die coating protecting the MEMS die and wire bonds.

Abstract: The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.

Abstract: Disclosed is a semiconductor device having a first transistor and a second transistor over the first transistor. The first transistor includes a first semiconductor, and the second transistor includes an oxide semiconductor that is different from the first semiconductor. A gate of the first transistor is electrically connected to a source or drain electrode of the second transistor. The second transistor has a semiconductor layer including the oxide semiconductor over the source and drain electrodes and a gate electrode over the semiconductor layer with an insulating layer therebetween.