Patents Examined by Trong Phan
  • Reference current sources
    Patent number: 8879327
    Abstract: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Russel J. Baker
  • Managing non-volatile media
    Patent number: 8873286
    Abstract: Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 28, 2014
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: John Strasser, David Flynn, Jeremy Fillingim, Robert Wood, Jea Hyun, Hairong Sun
  • Circuits and methods for providing data to and from arrays of memory cells
    Patent number: 8873314
    Abstract: A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Semiconductor memory device
    Patent number: 8867262
    Abstract: A semiconductor device includes plural memory cells each having a first inverter and a second inverter, with an input of the first inverter being coupled to an output of the second inverter and an input of the second inverter being coupled to an output of the first inverter. The first and second inverters have drive transistors supplied with a source voltage where the source voltage is raised in response to a level shift of a control signal supplied to a switch of a control circuit. The control circuit further includes a resistance element in parallel with a MOS transistor connected as a diode.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
  • Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory
    Patent number: 8854881
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 7, 2014
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
  • Configuring storage cells
    Patent number: 8854882
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes detecting a shift in a read voltage level past a read voltage threshold for a set of memory cells of a non-volatile memory medium. A method includes adjusting a read voltage threshold for the set of memory cells by an amount based at least in part on one or more characteristics of the set of memory cells in response to the shift in the read voltage level. A method includes configuring the set of memory cells to use the adjusted read voltage threshold.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 7, 2014
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: John Strasser, David Flynn, Jeremy Fillingim, Robert Wood
  • Operating method and data read method in nonvolatile memory device
    Patent number: 8837215
    Abstract: In a method of reading data in a nonvolatile memory device including data cells and monitoring cells. A first read operation applies a first read voltage to the data cells and monitoring cells. If a read fail occurs, a second read operation is performed using a read voltage level determined according to a number of ON-cells among the monitoring cells.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chul-Ho Lee
  • Semiconductor memory device and an operation method thereof
    Patent number: 8817557
    Abstract: A semiconductor memory device includes: a data transfer line coupled with a plurality of memory cell arrays corresponding to an address; an enable signal delayer configured to generate an enable signal by reflecting a delay amount corresponding to the address into an internal command signal corresponding to a column command; and a data exchange block configured to exchange data with the data transfer line in response to the enable signal.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jeongsu Jung
  • Semiconductor memory device having redundant fuse circuit
    Patent number: 8817560
    Abstract: A semiconductor memory device includes: a memory cell array configured to include a redundant cell array; a column selection line driver configured to select and drive a column of the redundant cell array and a column of the memory cell array; a plurality of unit redundant fuse circuits each configured to include a fuse and a fuse latch; a comparison logic array configured to include comparison logics that respectively correspond to the unit redundant fuse circuits; and a global address line set configured to transfer a column address to the comparison logic array.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jeongsu Jung
  • E-fuse array circuit and programming method of the same
    Patent number: 8817518
    Abstract: A program method for an e-fuse array circuit includes receiving an address and a multi-bit program data, programming the multi-bit program data in e-fuses designated by the address, reading a multi-bit read data from the e-fuses, and comparing bits of the multi-bit program data with bits of the multi-bit read data, wherein if the bits of the multi-bit program data are identical to the bits of the multi-bit read data, a program operation is terminated; and if the bits of the multi-bit read data are not identical to the bits of the multi-bit program data, then the programming of the multi-bit program data, the reading of the multi-bit read data, and the comparing of the bits are performed again.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyunsu Yoon, Yongho Seo
  • Nonvolatile semiconductor memory device and method for erasing data thereof
    Patent number: 8817538
    Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Kunihiro Yamada, Yoshihisa Iwata
  • Methods and systems for detecting and correcting timing signal drift in memory systems
    Patent number: 8804441
    Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 12, 2014
    Assignee: Marvell International Ltd.
    Inventor: Ross Swanson
  • Data storage system with power cycle management and method of operation thereof
    Patent number: 8792273
    Abstract: A method of operation of a data storage system includes: providing a power monitor module for detecting a loss of host power; interrupting a unit controller by the power monitor module; configuring a memory controller by the unit controller; and writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Smart Storage Systems, Inc.
    Inventors: Robert W. Ellis, Scott Creasman
  • Memory cell operation
    Patent number: 8787090
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Seiichi Aritome
  • Magnetic memory element with multi-domain storage layer
    Patent number: 8780619
    Abstract: An apparatus and method for storing data in a semiconductor memory. In accordance with some embodiments, the semiconductor memory has a continuous storage layer of soft ferromagnetic material having opposing top and bottom surfaces with overall length and width dimensions and an overall thickness dimension between the opposing top and bottom surfaces. A plurality of spaced apart, discrete reference layers are adjacent a selected one of the opposing top or bottom surfaces of the continuous storage layer with each having a fixed magnetic orientation. A plurality of spaced apart, discrete barrier layers are disposed in contacting relation between the discrete reference layers and the continuous storage layer.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 15, 2014
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Yuankai Zheng, Xiaobin Wang, Dimitar V. Dimitrov, Pat J. Ryan
  • Remote welding system and method
    Patent number: 8779329
    Abstract: Embodiments of a pendant associated with a multi-process welding power supply that allows a user to switch processes and reverse an output polarity while located remotely from a power supply unit are provided. Certain embodiments include a pendant with a wire spool and wire feeder drive circuitry that is configured to activate spooling during MIG welding. Control circuitry that may include processing circuitry and memory is provided. The control system may disable redundant controls on the power supply unit user interface when the power supply unit is connected to the pendant via a supply cable. Additionally, the control system may set the process, set the polarity, enable or disable a wire feed, and enable or disable gas flow according to inputs received via a user interface on either the power supply unit or the pendant.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: July 15, 2014
    Assignee: Illinois Tool Works Inc.
    Inventors: James Francis Rappl, Thomas D. Lahti, Jeffery R. Ihde, Joseph Edward Feldhausen
  • Clock generator
    Patent number: 8779811
    Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 15, 2014
    Inventors: Marco Passerini, Stefano Surico
  • Semiconductor memory device
    Patent number: 8780646
    Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: July 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Mi Kim
  • Semiconductor memory device and method of operating the same
    Patent number: 8767480
    Abstract: A semiconductor memory device includes a count clock generation unit for generating a count clock in response to a clock signal and a dummy count clock, a column address generation unit for generating a column address in response to the count clock, and a Y decoder for sending data, stored in a page buffer unit, to a data line in response to the column address.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: July 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sang Oh Lim, Ho Youb Cho
  • Configurable module and memory subsystem
    Patent number: 8767430
    Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: July 1, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Peter Gillingham, Roland Schuetz