Patents Examined by Trong Phan
  • Far end resistance tracking design with near end pre-charge control for faster recovery time
    Patent number: 8767494
    Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Lin Yang, Chung-Yi Wu, Yu-Hao Hsu
  • Semiconductor memory device and driving method thereof
    Patent number: 8767479
    Abstract: A semiconductor memory device using a termination scheme in a global data line includes a global data line and a data line drive unit. The global data line transfers data between an interface region and a plurality of core regions each having a memory bank. The data line drive unit is disposed in each of the core regions, and drives the data global line in response to data in a data transfer operation. The data line drive unit sets the global data line to a termination voltage level in a termination operation.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Woong Yun
  • Non-volatile memory device and related read method
    Patent number: 8755224
    Abstract: A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-jin Yun, Sang-chul Kang, Seung-jae Lee
  • Resistive switching for non volatile memory device using an integrated breakdown element
    Patent number: 8750020
    Abstract: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: June 10, 2014
    Assignee: The Regents of the University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo
  • Racetrack memory with low-power write
    Patent number: 8750013
    Abstract: Methods for writing include applying a current pulse to a racetrack memory medium to position a domain in proximity to a thermally triggered magnon source in contact with the racetrack memory medium; activating a heat source/sink in contact with the magnon source to create a thermal gradient in the magnon source, generating a magnon flow in the magnon source; and changing a magnetization in the racetrack memory medium by spin torque transfer from the magnon flow.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Anthony J. Annunziata
  • Racetrack memory with low-power write
    Patent number: 8750012
    Abstract: Racetrack memory units and methods for writing include a racetrack memory medium; a heat source/sink configured to change temperature according to an applied current; and a magnon source material in contact with the racetrack memory medium and the heat source/sink, such that a temperature of the heat source/sink causes a magnon flow in the magnon source material that injects a domain wall in the racetrack memory medium.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Anthony J. Annunziata
  • Semiconductor memory device
    Patent number: 8743639
    Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 3, 2014
    Assignee: SK Hynix Inc.
    Inventors: Woong Ju Jang, Kyu Nam Lim
  • Semiconductor memory device
    Patent number: 8743587
    Abstract: According to one embodiment, a semiconductor memory device includes first cells, first lines, second lines, a first cell array, and a signal driver. The first cell has in either a first state or a second state. Retention time in the second state is longer than in the first state. The first cell array has the first cells formed in a matrix the individuals. The first cells are electrically connected by the first, second lines. The signal driver drives the first cells. The signal driver causes the first cells to transition to either the first state or the second state by controlling any one of a voltage, a current, and a charge amount applied to the first cells, or a combination of these, and waveforms of the voltage, current, and charge amount and/or the length of transfer time of at least one of the voltage, current, and charge amount.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoru Takase
  • Natural threshold voltage distribution compaction in non-volatile memory
    Patent number: 8743606
    Abstract: In a non-volatile memory system, a programming operation applies programming pulses to a target word line, determines when a specified number of the non-volatile storage elements reach a defined verify level, and counts a specified number of the programming pulses after the specified number of the non-volatile storage elements reach the defined verify level. Upon completion of the counting, faster-programming storage elements are distinguished from slower-programming storage elements. Programming continues for of at least some of the faster-programming non-volatile storage elements, with an associated programming speed-based slow down measure imposed thereon, and for at least some of the slower-programming non-volatile storage elements without imposing a programming speed-based slow down measure.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: June 3, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepanshu Dutta, Jeffrey W Lutze
  • Non-volatile semiconductor memory device
    Patent number: 8743611
    Abstract: A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Hioka
  • SRAM cell having an N-well bias
    Patent number: 8724375
    Abstract: A method for writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. The method may include adjusting a bias level of the n-wells that contain the bit driver, bit-bar driver, bit passgate, and optional bit-bar passgate.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 13, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Seshadri, Theodore W. Houston
  • Nonvolatile semiconductor memory device
    Patent number: 8724383
    Abstract: A control circuit controls erase operation to erase data of memory transistors, correction write operation, and correction write verify operation. In the correction write operation, a erase threshold level of a memory transistor is moved to a positive threshold level after the erase operation. In the correction write verify operation, whether or not a threshold level of the result of the correction write operation reaches a first value is determined. In the correction write operation, the control circuit executes the correction write operation with respect to plural memory units connected to a common one of the bit lines as a group. The control circuit sequentially executes the correction write verify operation with respect to plural memory units in which the correction write operation is executed.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Iwai
  • Semiconductor memory device
    Patent number: 8717816
    Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 6, 2014
    Assignee: Windbond Electronics Corp.
    Inventor: Masaru Yano
  • Method and apparatus for leakage suppression in flash memory in response to external commands
    Patent number: 8717813
    Abstract: Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 6, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Nai-Ping Kuo, Su-Chueh Lo, Kuen-Long Chang, Chun-Hsiung Hung, Chia-Feng Cheng, Ken-Hui Chen, Yu-Chen Wang
  • Memory dies, stacked memories, memory devices and methods
    Patent number: 8717796
    Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Yutaka Ito
  • Data paths using a first signal to capture data and a second signal to output data and methods for providing data
    Patent number: 8711639
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Lee Eric
  • Resistive random access memory cell and resistive random access memory module
    Patent number: 8711601
    Abstract: A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen
  • Current mode sense amplifier with passive load
    Patent number: 8705304
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak
  • Quantifying the read and write margins of memory bit cells
    Patent number: 8705268
    Abstract: Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 22, 2014
    Assignee: Broadcom Corporation
    Inventors: Myron Buer, Carl Monzel, Yifei Zhang
  • Integrated circuit, method for driving the same, and semiconductor device
    Patent number: 8705267
    Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Endo, Takuro Ohmaru