Patents Examined by Trong Phan
  • Patent number: 9224432
    Abstract: In a semiconductor package, a circuit pattern is arranged in a circuit board and contact pads on the circuit board are connected with the circuit pattern. Contact terminals contact external contact elements on a first surface of the circuit board. An integrated circuit (IC) chip structure is mounted on the circuit board and electrically connected to the inner circuit pattern. An operation controller on the circuit board controls operation of the semiconductor package according to the package users' individual choice.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chul Park
  • Patent number: 9224501
    Abstract: A memory device includes a control logic configured to control an overall operation of the memory device; a data storing unit configured to receive write data and write the write data according to control of the control logic and to output read data obtained by reading the write data; and a detector configured to repeatedly generate a comparison result based on the read data and a current determination result based on the comparison result and a previous determination result N times and to generate a final determination result according to a result of the repetition, where N is an integer of at least 2. The final determination result indicates whether an error has occurred and a type of the error.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: December 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeong Sik Kong
  • Patent number: 9224481
    Abstract: A semiconductor storage device restraining the variation in threshold voltage of a memory unit is provided. The steps of the programming method for a flash memory include: setting a bit line to a program voltage or a program-protection voltage; applying a program pulse to the selected page; and verifying the programming of the selected page. Also, the steps further include: when the verification result indicates that there is a failed-shift memory cell which was passed previously but is failed presently, setting the voltage of the bit line of the failed shift memory to a mitigation voltage for mitigating the voltage of the next program pulse.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 29, 2015
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Masaru Yano
  • Patent number: 9208897
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for configuring storage cells. A method includes determining a usage history for a set of storage cells of a solid-state storage medium. A method includes adjusting a voltage threshold for a set of storage cells by an amount based at least in part on a usage history. A method includes configuring a set of storage cells to use an adjusted voltage threshold.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: December 8, 2015
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: John Strasser, David Flynn, Jeremy Fillingim, Robert Wood
  • Patent number: 9208855
    Abstract: A static random access memory (SRAM) is provided. The SRAM includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar during an entire duration of operation of the SRAM.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: December 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Cheng Hung Lee
  • Patent number: 9202580
    Abstract: The memory cells storing a group of codewords are read to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The components of each read signal are ordered according to signal level to produce an ordered read signal. Correspondingly-positioned components of the ordered read signals are then ordered according to signal level to produce ordered component sets for respective component positions in a said ordered read signal. Each ordered component set is partitioned into subsets corresponding to respective memory cell levels, wherein the subsets of the ordered component sets contain respective numbers of components dependent on predefined probabilities of occurrence of different symbol values at different positions in a said codeword whose symbols are ordered according to symbol value. The reference signal level is determined in dependence on the signal components in the subsets corresponding to that memory cell level.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: December 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Patent number: 9190161
    Abstract: According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k?1 levels (k?n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Noboru Shibata
  • Patent number: 9190162
    Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jun Xu
  • Patent number: 9183900
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eric Lee
  • Patent number: 9183894
    Abstract: The memory device includes a first logic element which is supplied with a first power supply voltage, and inverts a polarity of a potential of an input terminal to output the potential with the inverted polarity from an output terminal, a second logic element which is supplied with a second power supply voltage supplied through a different path from the first power supply voltage, and inverts a polarity of a potential of an input terminal to output the potential with the inverted polarity from an output terminal, a first memory circuit connected to the input terminal of the first logic element, and a second memory circuit connected to the input terminal of the second logic element. The input terminal and the output terminal of the first logic element are connected to the output terminal and the input terminal of the second logic element, respectively.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: November 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 9183931
    Abstract: Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kyu Lee, Dae-Won Kim
  • Patent number: 9177662
    Abstract: A pre-reading method and a programming method for a 3D NAND flash memory are provided. The pre-reading method comprises the following steps. A selected string includes a first memory cell, two second memory cells and a plurality of third memory cells. The two second memory cells are adjacent to the first memory cell. The third memory cells are not adjacent to the first memory cell. A first pass voltage is applied on the second memory cells, a second pass voltage is applied on the third memory cells, and a read voltage is applied on the first memory cell via a plurality of word lines for reading a data of the first memory cell. The first pass voltage is larger than the second pass voltage.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: November 3, 2015
    Assignee: MACRONIX INTERNAITONAL CO., LTD.
    Inventors: Wen-Wei Yeh, Chih-Shen Chang, Kuo-Pin Chang
  • Patent number: 9171620
    Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 27, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Nga Yee Avila, Yingda Dong, Alexander Kwok-Tung Mak, Steven T. Sprouse
  • Patent number: 9171623
    Abstract: A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoo Hishida, Yoshihisa Iwata, Yoshiaki Fukuzumi
  • Patent number: 9165672
    Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 20, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongku Kang, Dae Yeal Lee
  • Patent number: 9165657
    Abstract: An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Jin Yun, Bogeun Kim
  • Patent number: 9159407
    Abstract: A method includes storing data in a group of analog memory cells by writing respective analog values into the memory cells in the group. After storing the data, the analog values are read from the memory cells in the group one or more times using one or more respective read thresholds so as to produce readout results. Reliability measures are computed for the read analog values based on the readout results. An offset of the one or more read thresholds from an optimal read threshold position is estimated based on the reliability measures. The reliability measures are modified to compensate for the estimated offset, and the data stored in the analog memory cells in the group is decoded using the corrected reliability measures.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 13, 2015
    Assignee: Apple Inc.
    Inventors: Tomer Ish-Shalom, Ronen Dar
  • Patent number: 9159401
    Abstract: A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 13, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kyoichi Nagata
  • Patent number: 9142295
    Abstract: A content addressable memory includes a memory array having a plurality of match lines extending in a first direction, a plurality of search lines extending in a second direction perpendicular to the first direction, and a plurality of memory cells, each disposed at points where the match lines and the search lines intersect. The content addressable memory also includes a plurality of search line drivers, each of the search line drivers being provided to drive the search lines based on search data; a search control circuit generating a search line enable signal, and including a first and a second transistor, the first transistor) for output the search line enable signal and the second transistor for receiving the search line enable signal; and a control signal wiring coupled to the search control circuit and transmitting the search line enable signal to each of the search line drivers.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 22, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoya Watanabe
  • Patent number: 9135989
    Abstract: Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 15, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Manabu Sakai, Toru Miwa, Tien-chien Kuo