Patents Examined by Trong Phan
  • Semiconductor memory device and method of operating the same
    Patent number: 9053793
    Abstract: The semiconductor memory device includes a memory cell array configured to include a plurality of blocks, wherein each of the blocks has pages and each of the pages includes memory cells, and a peripheral circuit configured to program the memory cells to target program states. Here, the peripheral circuit programs the memory cells to temporary program states by applying program voltages increasing step-by-step by a first incremental value, and then programs the memory cells to the target program states by applying program voltages increasing step-by-step by a second incremental value.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 9, 2015
    Assignee: SK Hynix Inc.
    Inventor: Do Young Kim
  • Resistive switching for non volatile memory device using an integrated breakdown element
    Patent number: 9048658
    Abstract: A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: June 2, 2015
    Assignee: The Regents of The University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo
  • Erased state reading
    Patent number: 9047974
    Abstract: A method of determining whether a page of NAND flash memory cells is in an erased condition includes applying a first set of read conditions to identify a first number of cells having threshold voltages above a discrimination voltage under the first set of read conditions, if the first number of cells is less than a first predetermined number, applying a second set of read conditions that is different from the first set of read conditions to identify a second number of cells having threshold voltages above the discrimination voltage under the second set of read conditions, and if the second number of cells exceeds a second predetermined number, marking the page of flash memory cells as partially programmed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 2, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jianmin Huang, Zhenming Zhou, Gautam Ashok Dusija, Chris Nga Yee Avila, Dana Lee
  • Resistive random access memory device, method for manufacturing the same, and method for operating the same
    Patent number: 9047937
    Abstract: A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 2, 2015
    Assignee: Peking University
    Inventors: Jinfeng Kang, Bin Gao, Yuansha Chen, Bing Sun, Lifeng Liu, Xiaoyan Liu
  • Semiconductor device, data programming device, and method for improving the recovery of bit lines of unselected memory cells for programming operation
    Patent number: 9019765
    Abstract: A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: April 28, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Diego Della Mina, Osama Khouri, Chiara Missiroli
  • Semiconductor devices and semiconductor systems including the same
    Patent number: 9013932
    Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs offset signals whose level combination is controlled according to temperature code signals including information on an internal temperature. The semiconductor device generates the temperature code signals according to a level combination of the offset signals. Further, the semiconductor device controls a refresh cycle time determined by the level combination of the offset signals.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang Hoon Lee
  • Sense amplifier
    Patent number: 9013940
    Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Atul Katoch, Mayank Tayal, Cormac Michael O'Connell
  • Data randomization in 3-D memory
    Patent number: 9013919
    Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: April 21, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chris Avila, Yingda Dong, Lee Gavens
  • Methods for programming a memory device and memory devices
    Patent number: 9007832
    Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin
  • Semiconductor memory device having faulty cells
    Patent number: 9007830
    Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Solid State Storage Solutions, Inc.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Far end resistance tracking design with near end pre-charge control for faster recovery time
    Patent number: 9007859
    Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Lin Yang, Chung-Yi Wu, Yu-Hao Hsu
  • Semiconductor apparatus, test method using the same and muti chips system
    Patent number: 9001547
    Abstract: A semiconductor apparatus includes a test unit including: a data determination unit configured to receive a plurality of data, determine whether the plurality of data are identical or not, and output the determination result as a compression signal; and an output control unit configured to output the compression signal as a test result in response to a test mode signal and a die activation signal.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dae Suk Kim
  • Small-grain three-dimensional memory
    Patent number: 9001555
    Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: April 7, 2015
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Semiconductor integrated circuit
    Patent number: 8995174
    Abstract: A semiconductor device includes NAND gates and switches to form a circuit to hold data, and a capacitor electrically connected to the circuit via a transistor to store the data held in the circuit. The transistor has a channel formation region including an oxide semiconductor.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Memory with an assist determination controller and associated methods
    Patent number: 8982651
    Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 17, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Anuj Grover, Gangaikondan Subramani Visweswaran
  • Managing non-volatile media
    Patent number: 8982619
    Abstract: Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: March 17, 2015
    Assignee: Intelligent Intellectual Property Holdings 2 LLC
    Inventors: John Strasser, David Flynn, Jeremy Fillingim, Robert Wood, Jea Hyun, Hairong Sun
  • Nonvolatile semiconductor memory device
    Patent number: 8982623
    Abstract: A non-volatile semiconductor memory device has memory cell arrays, with the memory cells arranged in a matrix configuration and divided into p areas in the column direction, a column redundancy area arranged in a portion of the memory cell array and having redundancy columns that can substitute for defective user data columns, and a column substituting register that holds the column substituting information for substituting the defective user data columns of the selected area with the redundancy columns.
    Type: Grant
    Filed: March 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masanobu Shirakawa
  • Memory system and related method of operation
    Patent number: 8976580
    Abstract: A memory system comprises a nonvolatile memory and a phase change memory. The memory system can be operated by reading operation information of the nonvolatile memory from the phase change memory, adjusting voltage parameters of the nonvolatile memory based on the read operation information, and performing an operation of the nonvolatile memory based on the adjusted voltage parameters.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Ho Lee, Seijin Kim
  • Semiconductor apparatus
    Patent number: 8976567
    Abstract: A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dong Keun Kim
  • Flash memory device and method of programming the same
    Patent number: 8976584
    Abstract: A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinman Han, Ho-Chul Lee, Min-Su Kim, Sangwan Nam, Junghoon Park