Patents Examined by Tuan Dinh
  • Patent number: 6876553
    Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: April 5, 2005
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Reza-ur Rahman Khan, Imtiaz Chaudhry
  • Patent number: 6876554
    Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: April 5, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 6870741
    Abstract: A system for reducing an apparent height of a board system is provided. The board system may include, for example, a carrier, a component, a printed circuit board and/or a solder material. The component is mounted on a first side of the carrier. The printed circuit board has a hole that is structured to accommodate the component. The solder material solders the carrier to the printed circuit board and provides a structural bond between the carrier and the printed circuit board. At least one portion of the solder material provides an electrical coupling between the carrier and the printed circuit board and at least one portion of the component is maintained in the hole after the carrier is soldered to the printed circuit board.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 22, 2005
    Assignee: Kyocera Wireless Corp.
    Inventor: Paul Aurelio Martinez
  • Patent number: 6864435
    Abstract: A flexible electronic, Radio Frequency Identification (RF ID) or display device and methods of making the same. The flexible electronic, Radio Frequency Identification (RF ID) or display device comprises a flexible substrate having a top surface and a bottom surface. The top surface comprises electrical components. The flexible substrate comprises openings cutting therethrough from the top surface to the bottom surface. A conductive layer is coupled to the flexible substrate wherein the openings expose at least a portion of the conductive layer. The openings are filled with conductive elements to make first electrical contacts to at least a portion of the conductive layer and second electrical contacts to the electrical components on the flexible substrate.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: March 8, 2005
    Assignee: Alien Technology Corporation
    Inventors: Anno Hermanns, Randolph W. Eisenhardt, Glenn W. Gengel
  • Patent number: 6865089
    Abstract: A module board has embedded chips and components. A substrate has at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first adhesion layer bonds the bottom of the substrate to the heat-dissipation sheet. At least one IC chip is fixed in the large cavity of the substrate by a second adhesion layer. A dielectric filling layer covers the entire surface of the module board and fills all gaps, in which the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate. At least one wiring pattern layer is formed on the dielectric filling layer and provide electrical connection among the IC chip, the passive component, and the substrate.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: March 8, 2005
    Assignee: Via Technologies, Inc.
    Inventors: Kwun Yao Ho, Moriss Kung
  • Patent number: 6862191
    Abstract: A miniaturized microelectronic, hybrid circuit package having either a single or a multi-layer, flexible, printed circuit substrate with printed conductors interconnecting a plurality of integrated circuit (IC) dies with a ball grid array (BGA) of contacts. The IC dies are arranged on parallel strips defined between preferential fold zones formed in the substrate. The dies are over molded with plastic that is shaped to facilitate the substrate being folded to form a polyhedron. When so folded, the over molded IC dies face inward and BGA is exposed on an outwardly facing surface to facilitate attachment of the folded package to a motherboard.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: March 1, 2005
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Nick Youker, Ronald L. Anderson, John E. Hansen, Melburn Kjear
  • Patent number: 6862192
    Abstract: A printed circuit board wiring system including a printed wiring circuit board having a plurality of conductive layers, at least one electronic part mounted on one side of the circuit board and configured to output signals via signal lines, and an auxiliary wiring package mounted on the other side of the circuit board and including a plurality of conductive layers configured to allow the signal lines from the electronic part to pass therethrough so as to be connected to the circuit board. Further, a first set of signal lines are immediately drawn from the at least one electronic part using half of the plurality of conductive layers of the circuit board without passing through the auxiliary wiring package, and a second set of signal lines are drawn from the at least one electronic part through the circuit board and the auxiliary wiring package using the other half of the plurality of conductive layers of the circuit board.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: March 1, 2005
    Assignee: Ricoh Company, Ltd.
    Inventor: Akira Yashiro
  • Patent number: 6855891
    Abstract: A card edge connector comprises a connector body and a conductive pad, and is constructed such that the conductive pad terminates at a predetermined distance from the end of the tip portion of the connector body, and that there is further provided a protective pad, adjacent to the terminating portion of the conductive pad, which is formed at the same time with the formation of a wiring pattern in a post-fabrication step of the wiring pattern. Using the card edge connector, an electric card and an electric equipment are also provided.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Susumu Eguchi, Hiroshi Shimamori
  • Patent number: 6850415
    Abstract: An electronics cabinet is described as being suitable for use in an aircraft. Various embodiments of the cabinet include a databus that facilitates data communications between circuit boards inserted into the cabinet. The cabinet also preferably includes access holes that allow inserted circuit boards to connect directly to an aircraft wiring harness.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: February 1, 2005
    Assignee: Honeywell International Inc.
    Inventor: Mario Dimarco
  • Patent number: 6847529
    Abstract: A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: January 25, 2005
    Assignee: INCEP Technologies, Inc.
    Inventors: Joseph Ted Dibene, II, David H. Hartke, Carl E. Hoge, Edward J. Derian
  • Patent number: 6845017
    Abstract: A DC bus for use in a power module includes a positive DC conductor bus plate parallel with a negative DC conductor bus plate. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: January 18, 2005
    Assignee: Ballard Power Systems Corporation
    Inventors: Sayeed Ahmed, Scott Parkhill, Fred Flett, Douglas Maly
  • Patent number: 6845016
    Abstract: An electronic device includes: a substrate; a plurality of operating elements provided in an operating region of the substrate; a first wiring pattern which is provided outside the operating region in the substrate so that the first wiring pattern has the width longer than the operating region; a first electrode formed in a layer different from the first wiring pattern, partially overlapping the first wiring pattern, and supplying common electrical energy to the operating elements; and a conductive section provided in a region in which the first wiring pattern partially overlaps the first electrode, electrically connecting the first wiring pattern to the first electrode.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: January 18, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Yojiro Matsueda
  • Patent number: 6842346
    Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: January 11, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kyouichi Takagawa, Kozo Sakamoto, Nobuyoshi Matsuura, Masashi Koyano
  • Patent number: 6841740
    Abstract: A printed-wiring substrate including a capacitor element, as well as a method for fabricating the printed-wiring substrate. An insulating substrate 3 is molded by placing a capacitor element 13 in a mold and charging a resin 4 into the mold. Therefore, the capacitor element 13 having a size (i.e., electrostatic capacitance) sufficient to suppress switching noise of an IC chip 15 and stabilize operation power voltage can be disposed, while providing a dimensional margin. Since the possibility of failing to embed the capacitor element 13 decreases, the printed-wiring substrate can be fabricated at reduced cost.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: January 11, 2005
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kouki Ogawa, Eiji Kodera
  • Patent number: 6839241
    Abstract: A circuit module comprises a circuit board having a plurality of contact elements along a longitudinal edge thereof. The circuit board has arranged thereon a SDRAM memory component, the connections of this SDRAM memory component being each connected via resistance elements, which are implemented as individual resistors, to one of the contact elements through lines of limited length. The individual resistors are arranged in a line which extends parallel to the longitudinal direction of the circuit board.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: January 4, 2005
    Assignee: Infineon Technologies AG
    Inventors: Martin Benisek, Wolfgang Hoppe, Martin Schober
  • Patent number: 6833512
    Abstract: A substrate board structure having a core layer, a metallic layer and a connecting metallic layer. The core layer has a first surface and a second surface. The metallic layer includes a contact pad and a circuit line. The contact pad and the circuit line are separately lain on the first surface of the core layer. The connecting metallic layer is formed on the second surface of the core layer. The connecting metallic layer is electrically connected to both the contact pad and the circuit line.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: December 21, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Sheng-Tsung Liu
  • Patent number: 6833511
    Abstract: A molded interconnect device (MID) having a multilayer circuit of a reduced thickness, in which a layer-to-layer connection(s) is formed with high reliability, is provided as a multilayer circuit board. The multilayer circuit board comprises a substrate having a first surface and a second surface extending from an end of the first surface at a required angle relative to the first surface, and the multilayer circuit formed on the first surface and composed of a plurality of circuit layers. Each of the circuit layers is provided with a conductive layer having a required circuit pattern and an insulation layer formed on the conductive layer by film formation. The layer-to-layer connection of the multilayer circuit is made through a second conductive layer formed on the second surface of the substrate.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 21, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yoshiyuki Uchinono, Kazuo Sawada, Yasufumi Masaki, Masahide Muto
  • Patent number: 6833998
    Abstract: A circuit board assembly includes first and second circuit board devices. The first circuit board device includes a printed circuit board, a first controller mounted on the first printed circuit board, and a first communications unit mounted on the first printed circuit board and that is connected electrically to the first controller. The second circuit board device includes a second printed circuit board separate from the first printed circuit board, a second controller mounted on the second printed circuit board, and a second communications unit mounted on the second printed circuit board and connected electrically to the second controller. The second communications unit cooperates with the first communications unit to establish a communications link between the first and second controllers while maintaining separability between the first and second printed circuit boards.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: December 21, 2004
    Assignee: Compal Electronics, Inc.
    Inventors: Wei-Pin Chuang, Chih-Chuan Cheng
  • Patent number: 6833997
    Abstract: A circuitboard assembly in which power carrying circuitboard traces between MOSFETs or the like and edge terminals are replaced with metal leadframe structures which also serve to perform a heat dissipation function. Each of the leadframes comprises a first planar portion which is bonded by a thermally conductive epoxy to the top surface of a MOSFET and a second elevated planar portion which extends parallel to but above the circuitboard surface into contact with an edge-mounted terminal header. The leadframes may be provided with support legs as well as additional heat dissipating fins.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: December 21, 2004
    Assignee: Yazaki North America, Inc.
    Inventors: James L. Jones, III, Truong Nguyen, Martin Eugene Beckman
  • Patent number: 6831841
    Abstract: A first driver IC is mounted in the area which includes one side of the panel substrate on an electro-optical panel, and the edge portion of the film base material on which a second driver IC is mounted is bonded to the vicinity of the one side of the above-mentioned panel substrate. Also, driver-controlling electronic components which each provides control signals to the first and second driver ICs are mounted on the same surface as the second driver IC in the film base material.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: December 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Oishi, Masanori Yumoto, Yasuhito Aruga