Patents Examined by Tuan Dinh
  • Patent number: 6914200
    Abstract: A multilayer wiring board assembly, a multilayer wiring board assembly component and a method of manufacture thereof are described in which it is possible to easily laminate together flexible FPCs having highly packing densities by via-on-via and chip-on-via. The multilayer wiring board assembly is laminated by laminating together a plurality of multilayer wiring board assembly components, each of which is made by preparing a copper plated resin film 10 made of a copper plated resin film made of a resin film having adhesivity which is provided with a copper foil bonded to one surface thereof and in which a through hole is opened through said copper foil and said resin film, and a conductive paste filler embedded by screen printing in the through hole of said copper plated resin film from said copper foil with a leading end of said conductive paste filler being projected from said resin film.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: July 5, 2005
    Assignee: Fujikura Ltd.
    Inventors: Reiji Higuchi, Shouji Itou, Osamu Nakao
  • Patent number: 6912134
    Abstract: A dual output power module housing a dual output power circuit for providing variable power to two parallel connected fan motors is shown. The power module includes a pad which has disposed thereon two power switching devices, two intelligent power switches, and a power circuit board on which circuits for controlling the intelligent power switches are disposed. The module includes a power shell that surrounds the dual output power circuit, and a resilient, flexible enclosure which encapsulates the power shell and the circuit components within the power shell.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: June 28, 2005
    Assignee: International Rectifier Corporation
    Inventors: William R. Grant, Sergio Fissore
  • Patent number: 6909614
    Abstract: A multi-layer power backplane system is disclosed for use with various power electronic and other systems. The power backplane includes multiple mechanical, conductor and isolation layers which serve to route power to and from various components. The layers are isolated from one another by support/isolation panels which may receive conductors used to route power. Data signals may also be routed through the system. The system accommodates fluid cooling of the electronic components by an additional layer of conduit support and isolation. The overall system provides a high degree of flexibility and modularity in defining a power backplane for a wide range of circuitry and components which may be mounted thereto once the power backplane is designed and assembled.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: June 21, 2005
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Bruce C. Beihoff, Dennis L. Kehl, Timothy A. Roebke, Lee A. Gettelfinger
  • Patent number: 6909613
    Abstract: The present invention relates to an assembly comprising an electrical element, such as a coil, and especially to an assembly more easily assembled. Assemblies of this type are used for receivers for hearing aids or sound generators for e.g. mobile telephones.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: June 21, 2005
    Assignee: Sonionmicrotronic Nederland B.V.
    Inventors: Jeroen Augustijn, Onno Geschiere, Marcel de Blok
  • Patent number: 6909054
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: June 21, 2005
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Patent number: 6906928
    Abstract: The electronic component has a semiconductor chip mounted to a wiring board. The chip is bonded to the wiring board with adhesive strips that leave free a through-cutout, an additional cutout, and separating joints. The additional cutout provides for a plastic reservoir from which the separating joint between the adhesive strips is filled with plastic material.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 14, 2005
    Assignee: Infineon Technologies AG
    Inventors: Christian Hauser, Martin Reiss
  • Patent number: 6906929
    Abstract: A computer backplane is disposed with at least an AGP slot, a PCI slot and/or an EISA slot. The PCI slot can be used to electrically connect with PCI cards. The EISA slot and the PCI slot are in alignment to allow that a CPU card can be connected simultaneously to both the EISA slot and the PCI slot. The AGP slot is used to electrically connect with an AGP card. Such an arrangement allows for ease of replacement of the AGP card and a lower production cost.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 14, 2005
    Assignee: ICP Electronics Inc.
    Inventor: Tsai-Sheng Chiu
  • Patent number: 6903938
    Abstract: The invention relates to a printed circuit board comprising capacitive and inductive elements. To arrange such a printed circuit board so that it has a smaller thickness and can be manufactured cost effectively, a printed circuit board is proposed having at least one dielectric layer, on the two side faces of which capacitor electrodes arranged opposite each other are positioned in a first area and two planar windings opposite each other are arranged in at least a second area next to the first area on the side faces of the electric layer.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: June 7, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Eberhard Waffenschmidt
  • Patent number: 6903941
    Abstract: A printed circuit board (PCB) assembly includes a PCB and an electrical connector. The PCB includes a first major surface and an opposite second major surface. The electrical connector includes a connector component electrically coupled to the PCB. The connector component has a nonconductive body that is adapted to contact and be supported by a first major surface of the PCB.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: June 7, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jose Pietri Paola
  • Patent number: 6900394
    Abstract: A method is provided for removing plating blocking ions, such as anions, in pairs with copper ions and oxidant ions of a copper ion reducing agent from an electroless copper plating solution and keeping a constant salt concentration in the electroless copper plating solution during plating. The electroless copper plating method uses a plating solution containing copper sulfate as copper ion sources, and a copper ion complexing agent as copper ion sources, glyoxylic acid as a copper ion reducing agent, and a pH conditioner. The method is characterized by precipitating and removing sulfuric and oxalic ions in said electroless copper plating solution and keeping an optimum concentration of at least one of sulfuric and oxalic ions in said electroless copper plating solution during plating.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 31, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takeyuki Itabashi, Haruo Akahoshi, Tadashi Iida, Yoshinori Ueda, Eiji Takai, Naoki Nishimura
  • Patent number: 6900992
    Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: May 31, 2005
    Assignee: Intel Corporation
    Inventors: Christopher J. Kelly, Jeffrey L. Krieger, Raymond P. Askew
  • Patent number: 6894905
    Abstract: An “H layout” according to the present invention affords for a smaller, simpler, less expensive and higher performance midplane for use in a communication system for connecting various modules together. The layout is based on the concept of symmetry around a mid-section, which allows for the reuse of APM cards on the top and bottom of a midplane. All high-speed tracks on the midplane are concentrated in the center thereof. Front and back connectors on the midplane are staggered so as to permit very high module densities while maintaining manageable finger access. The present invention has the advantages of: reducing high-speed track lengths in a backplane or midplane; simplifying high speed track routing by having almost only horizontal tracks on the midplane, thus reducing crossing over; and providing a smaller midplane, thus reducing costs.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: May 17, 2005
    Assignee: Nortel Networks Limited
    Inventors: Rudy Vianna, Simon Richardson, Christopher S. Knapton
  • Patent number: 6891732
    Abstract: A multilayer circuit board for mounting a semiconductor element thereon, comprising a core substrate of a metal material and a plurality of wiring layers stacked on either side of the core substrate, each of the stacked wiring layers being isolated from an adjacent wiring layer by an insulating layer interposed therebetween, the multilayer circuit board having an area at which a heat spreader for dissipating heat generated from the semiconductor element mounted on the circuit board is to be joined to the multilayer circuit board, wherein the multilayer circuit board allows the heat spreader to be joined to the core substrate without the insulating layers being interposed therebetween. A semiconductor device using the multilayer circuit board is also disclosed.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: May 10, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akihito Takano, Takahiro Iijima
  • Patent number: 6884943
    Abstract: A thin, lightweight retention mechanism with a spring force holds an integrated circuit package to a circuit board. The retention mechanism consists of a pressure plate, a backing plate, and a fastening means for applying a deforming force to the plates, such as screws and nuts. The plates are paraboloid or dish-shaped and made of an elastically deformable material, such as steel. The fastening means simultaneously applies deforming forces to the peripheries of the plates to create a continuous spring force to effect electrical continuity between the integrated circuit package and the circuit board. In addition, a method of testing the retention mechanism and a method of assembling the retention mechanism are disclosed.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Carlos A. Gonzalez, Leo Ofman
  • Patent number: 6885562
    Abstract: A circuit package with improved heat dissipation properties for high-power circuits. In one embodiment, the circuit package comprises two circuit boards positioned in different planes, at least one brace affixed between the two circuit boards, a molded housing enclosing an area between the circuit boards, and a plurality of electrically conductive leads extending from the sides of the circuit package. The molded housing is configured to expose at least one surface of the circuit boards to the exterior surface of the circuit package. The leads are configured in a J-shape, which allows the circuit package to be mounted in an upright position. The brace functions as a flexible spacer for holding the two circuit boards in position during the application of the molded housing. In one embodiment, a H-bridge circuit is configured on the first and second circuit boards of the circuit package.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: April 26, 2005
    Assignee: Medtronic Physio-Control Manufacturing Corporation
    Inventors: Ronald G. McIlnay, Martin S. Abbbenhouse
  • Patent number: 6885563
    Abstract: Systems for power delivery, signal transfer, package design, thermal management, and electromagnetic interference (“EMI”) control are provided to support an integrated circuit (“IC”). The power delivery system includes a power supply, a voltage regulator module and a decoupling capacitance in the form of discrete and/or integral capacitors. The voltage regulator module and decoupling capacitance are located in a connector that may be formed as a cover, socket or a frame for the IC. The power delivery system delivers power to the IC along top, bottom or sides of the IC. The signal transfer system couples signals from the IC to one or more circuits on a circuit board. The package design system for the IC permits signals and/or power to be coupled to selected sides of the IC at connections outside, flush with, recessed or inside the IC package.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: April 26, 2005
    Assignee: Molex Incorporated
    Inventors: Augusto P. Panella, James L. McGrath
  • Patent number: 6882544
    Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: April 19, 2005
    Assignees: NEC Toppan Circuit Solutions, Inc., NEC Tokin Corporation
    Inventors: Hirofumi Nakamura, Satoshi Arai
  • Patent number: 6882546
    Abstract: A multiple integrated circuit (IC) die assembly includes a base IC die and secondary IC dice mounted on a surface of the base IC die. A set of protruding contacts formed on the surface of the base IC die and extending beyond the secondary IC dice link the surface of the base IC die to a printed circuit board (PCB) substrate with the secondary IC die residing between the base IC die and the PCB substrate.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: April 19, 2005
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Patent number: 6882542
    Abstract: An electronic apparatus comprises a function module having a multilayer wiring unit including a first signal wiring corresponding to an internal layer wiring, a first signal via, a first reference potential wiring, a first signal pad to which the first signal wiring is connected through the first signal via, a first reference potential pad that surrounds the periphery of the first signal pad and to which the first reference potential wiring is connected, and a first reference potential connected to the first reference potential pad; a inultilayer circuit board; a first conductor; and a second conductor.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 19, 2005
    Assignee: NEC Corporation
    Inventors: Naoya Tamaki, Norio Masuda, Toshihide Kuriyama, Masamoto Tago
  • Patent number: 6879493
    Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: April 12, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Suzushi Kimura, Tsuyoshi Himori, Koji Hashimoto