Abstract: A method of measuring the stress migration of vias, and a the structure, the method comprising the following steps. A metal line having a middle and opposing first and second ends is formed. First and second opposing pads electrically connected to the respective opposing first and second ends of the metal line through respective first and second step-width line structures are formed. A third pad connected to the metal line proximate its first end by a first via through a first metal structure is formed. A fourth pad connected to the metal line proximate its second end by a second via through a second metal structure is formed. The first and second vias are equidistant from the respective first and second ends of the metal line. The stress migration of the first via is determined by measuring the: sheet resistance between the first pad and the third pad; and/or the stress migration of the second via is determined by measuring the sheet resistance between the fourth pad and the second pad.

Abstract: A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A single sided silicon layer adjacent to the sidewall in the opening. The single sided silicon layer exposes a portion of the opening base surface. The single sided silicon layer is implanted with fluorine-containing ions. The substrate and the single sided silicon layer is thermally oxidized to form a thermal oxide layer in the opening.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses.

Abstract: A method of manufacturing a MIM capacitor which is characterized as follows. We provide a semiconductor structure having a first region and a capacitor region. Next we form a first conductive layer over the semiconductor structure. The first conductive layer is patterned to form a plurality of trenches in the capacitor region. We form a capacitor dielectric layer over the first conductive layer. We form a top plate over the capacitor dielectric layer in the capacitor region. The first conductive layer in the first region is patterned to form conductive patterns and a bottom plate. An interlevel dielectric layer is formed over the first conductive layer and top plate.

Abstract: A tool and method is described to decide partial wafer sizes to process multiple random sizes of wafers in pick and place equipment for wafermap operation. The tool identifies the wafer and gets wafermap data. The position of one or more cutters is displayed. The position of the cutters relative to the wafer is displayed. The tool generates and displaying the results of the type of dies in each partial that would result from a cut according to said displayed position of the cutters.

Abstract: A system and method for determining endpoint detection in semiconductor wafer planarization is provided. The system and method provide a flexible solution that can compensate for baseline variability induced errors that may otherwise occur in endpoint detection. The system uses an endpoint detection signal that monitors the optical characteristics of the wafer being planarized. The system and method continue to monitor the detection signal during planarization until it meets endpoint criterion that indicates endpoint completion. When the endpoint criterion is reached, a new snapshot is taken from a previous time period and a new baseline is calculated. The endpoint detection signal is then recalculated based upon the new baseline and the recalculated detection signal is again compared to the endpoint criterion. If the recalculated endpoint detection signal again substantially meets the endpoint criterion then the detection of endpoint is confirmed.

Abstract: Disclosed are a non-volatile memory device to protect a floating gate from charge loss and a method for forming the same. At least a pair of floating gate lines are formed on a semiconductor substrate. A portion of the substrate between the floating gate lines is etched to form a trench therein. A gap-fill dielectric layer is formed in the trench and also in the gap between the pair of floating gate lines. The gap-fill dielectric layer is implanted with impurities so that positive mobile ions that may permeate the floating gate through the gap-fill dielectric layer can be trapped in the gap-fill dielectric layer.

Abstract: A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode large area on the substrate wherein the cathode large area has a third width W″ and a length L″ that are both substantially larger than either of the first and second widths.

Abstract: A method of texturing a surface of a substrate, includes providing a substrate, and distributing separate particles of an overlayer material in a substantially random pattern over at least a part of a surface of the substrate. The substantially random pattern of separate particles is used as a mask for a subsequent processing of the substrate.

Abstract: Disclosed is a method for forming metal wiring in a semiconductor device. The method comprises forming a TiN thin layer on a semiconductor substrate by using Ti compound containing a halogen element which corresponds to a 17 group element in the periodic table and NH3 reactant and adsorbing halogen atoms to the surface of the TiN thin layer; and forming a copper (Cu) thin layer on the TiN thin layer by using the adsorbed halogen atoms as catalyst. Wiring can be carried out in situ in a single chamber system in order to obtain excellent interface characteristics and a short process time.

Abstract: A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (130) to protect the stack during the silicidation process.

Abstract: The method for fabricating a semiconductor device including a step of forming a gate insulation film on a semiconductor substrate 10, the method further comprises, before the step of forming the gate insulation film, the step of forming an insulation film 12, covering a first side (upper side) and a second side (underside) of the semiconductor substrate 10, the step of etching off the insulation film 12 on the first side of the semiconductor substrate 10, and the step of annealing the semiconductor substrate 10 with the insulation film 12 present on the second side of the semiconductor substrate 10.

Abstract: A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a semiconductor layer with a gate insulating layer interposed in between, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. The control gate includes a first control gate and a second control gate which are adjacent to each other. The first control gate is formed on a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: Further improvements in circuit-element performance of surface-acoustic wave devices are anticipated by being able to produce a diamond substrate on which is formed a Li(NbxTa1−x)O3 (wherein 0≦x≦1) thin film whose c-axis orientation is favorable and whose piezoelectric characteristics are satisfactory. A diamond substrate on which a highly c-axis oriented, piezoelectrically satisfactory Li(NbxTa1−x)O3 (wherein 0≦x≦1) thin film is formed can be obtained by using a laser ablation technique to form a Li(NbxTa1−x)O3 (wherein 0≦x≦1) thin film onto a (110)-oriented gas-phase synthesized polycrystalline diamond substrate, that is superficially mirror-surface processed. By utilizing a diamond substrate on which a piezoelectric-substance thin film is formed, surface-acoustic wave devices having high propagation speeds can be offered.

Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: A method is provided that allows a simple and inexpensive apparatus to measure the uniformity of the height-directional positions of spheres or hemispheres such as bump electrodes of a semiconductor device. The degree of focus is calculated from an image of bump electrodes 11a and 11b acquired at a first focusing position F1 using an imaging system. After that, the bump electrodes 11a and 11b and the imaging system is relatively moved closer or farther, and then the degree of focus is calculated from an image acquired at a second focusing position F2. The degrees of focus at these two focusing positions F1 and F2 are compared with each other. As a result, detected are the contour lines of the horizontal cross sections of the bump electrodes 11a and 11b at the height (F1+F2)/2 of the position of equal degree of focus indicated by PQ. On the basis of the shapes and/or sizes thereof, the height-directional positions of the bump electrodes 11a and 11b are measured.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.