Abstract: The present invention relates to an organic, colored, electroluminescent display having the following features: between two strip-shaped structured electrodes running transverse to each other, there is a functional layer of electroluminescent polymers that are delimited by the windows (10) of an insulating layer (5), the functional polymers define pixels of different colors R, G and B for a matrix, strip-shaped ridges of at least one additional insulating layer (15 and 20 in the case of two layers), which structure one of the electrodes, separate pixels of the same color from pixels of different colors, where pixels of the same color are located between two adjacent ridges.

Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.

Abstract: An OXO-type inter-poly insulator (where X is a high-K metal oxide and O is an insulative oxide) is defined by forming an amorphous metal oxide layer on a silicon-based insulator (e.g., a silicon oxide layer) and then nitridating at least upper and lower sub-layers of the amorphous metal oxide with a low temperature plasma treatment that maintains temperature below the recrystallization temperature of the amorphous material. Such a plasma treatment has been found to improve breakdown voltage characteristics of the insulator. In one embodiment, the metal oxide includes aluminum oxide and it is fluorinated with low temperature plasma prior to nitridation.

Abstract: CMP process control array groups are fabricated upon the surface of the wafer for viewing through an optical microscope. The array groups include a plurality of test arrays, where each array includes a plurality of projecting test features. Each of the projecting test features are formed with the same projecting height and have a hard upper surface layer, such as diamond-like-carbon (DLC). All of the projecting test features within an array are formed with the same diameter, and the diameter of projecting test features of a particular array differs from the diameter of projecting test features in another array. The diameters are chosen such that the DLC surface is removed in specifically designed time increments, such as 5 seconds, from array to array, where projecting test features with the DLC surface removed appear as bright white, while the arrays with test features that retain some DLC surface are significantly darker.

Abstract: A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.

Abstract: Disclosed herein are slurry compositions for use in CMP(chemical mechanical polishing) process of metal wiring in manufacturing semiconductor devices, comprising a peroxide, an inorganic acid, a propylenediaminetetraacetate(PDTA)-metal complex, a carboxylic acid, a metal oxide powder, and de-ionized water, wherein the PDTA-metal complex plays a major role in improving overall polishing performance and reproducibility thereof by preventing abraded tungsten oxide from readhesion onto the polished surface, as well as in improving the dispersion stability of the slurry composition.

Abstract: A method for forming a conductive layer is disclosed, which has the following steps. First, a substrate is provided, and then a patterned photoresist layer having an undercut is formed on the substrate. After that, at least one conductive layer is deposited on the substrate. Finally, the patterned photoresist layer is lifted off; wherein the shape of the conductive layer remaining on the substrate is complementary to that of the patterned photoresist layer.

Abstract: A process for the fabrication of devices that integrate protected microstructures, comprising the following steps: forming, in a body of semiconductor material, at least one microstructure having at least one first portion and one second portion which are relatively mobile with respect to one another and are separated from one another by at least one gap region, which is accessible through a face of the body; and sealing the gap. The sealing step includes depositing on the face of the body a layer of protective material, in such a way as to close the gap region, the protective layer being such as to enable relative motion between the first portion and the second portion of the microstructure.

Abstract: A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Abstract: A method for forming a polysilicon germanium layer on a gate oxide layer without forming a polysilicon seed layer previously is disclosed. The method uses a chemical vapor deposition process at a temperature range between about 500° C. to about 600° C. by using a Si2H6 (disilane) gas and a germanium-containing gas as precursors to form a polysilicon germanium layer on a gate dielectric layer as a gate electrode layer. The polysilicon germanium layer directly formed on the gate dielectric layer has a smooth surface.

Abstract: A process for underfilling a bumped die surface using a lamination step and compound film such that solder bumps on the die are exposed during lamination. The compound film comprises a first layer containing an underfill material and a second layer on the first layer. The underfill material and the second layer comprise polymer materials that differ from each other. The compound film is laminated to the die, preferably at the wafer level, so that the underfill material is forced between the solder bumps and fills spaces between the bumps but does not cover the bumps. In contrast, the second layer covers the solder bumps, but is then selectively removed to re-expose the solder bumps and the underfill material therebetween.

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 ? can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.

Abstract: A semiconductor device reduced in size is provided in which the surface area outside of a display portion required for IC chips to mounted is reduced in a semiconductor device having an active matrix display portion. Further, signal wiring connection defects that accompany IC chip mounting are reduced. By manufacturing TFTs on an opposing substrate in a reflecting active matrix semiconductor device, thus manufacturing a desired logic circuit, the logic circuit, conventionally mounted externally, is formed on the opposing substrate. Further, the semiconductor device is made high speed and high performance by using suitable TFT structures and electric power source voltages for pixels and driver circuits on a pixel substrate and for the logic circuit on the opposing substrate.

Abstract: A process for providing regions of substantially lower fluorine content in a fluorine-containing dielectric comprises exposing the fluorine-containing dielectric to a reactive species to form volatile byproducts.

Abstract: A semiconductor component includes a substrate, bonding pads on the substrate, and external contacts bonded to the bonding pads. Exemplary external contacts include solder balls, solder bumps, solder columns, TAB bumps and stud bumps. Preferably the external contacts are arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The component also includes a polymer support member configured to strengthen the external contacts, absorb forces applied to the external contacts, and prevent separation of the external contacts from the bonding pads. In a first embodiment, the polymer support member comprises a cured polymer layer on the substrate, which encompasses the base portions of the external contacts. In a second embodiment, the polymer support member comprises support rings which encompass the base portions of the external contacts.

Abstract: Processes that may be used in producing electronic, optoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor material having a thickness of plural thin layers onto a support layer of. The semiconductor material for the support layer may be selected to be less precious or to have a lower quality than the donor layer. The support layer may have sufficient mechanical characteristics for supporting the donor layer during desired semiconductor processing treatments.

Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

Abstract: First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.

Abstract: Disclosed are a liquid crystal display device and a method for manufacturing the same, in which wirings connected between pads and an integrated circuit is protected from being corroded. A pixel array is formed on a display region of a substrate. A plurality of pads are formed on a non-display region of the substrate. An integrated circuit is formed on the non-display region of the substrate and connected to the pads to generate a signal for operating the pixel array. Conductive barrier layers separated from each of the pads are formed on peripheral portions of the pads connected to the integrated circuit. The conductive barrier layers have electric potential equivalent to that of each of the pads in accordance with internal connections of the integrated circuit. When bumps of the integrated circuit and the pads are attached to each other, the conductive barrier layers prevent the pads and the wirings connected to the pads from being corroded.

Abstract: A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.