Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.

Abstract: Embodiments include semiconductor devices and methods of manufacture, one of which includes a capacitor unit formed on a silicon substrate. The capacitor unit is divided into a plurality of capacitor subunits which are partitioned from each other by a separating insulation layer. Each of the capacitor subunits includes a first electrode layer composed of an impurity diffusion layer formed in the silicon substrate, a second electrode layer composed of a conductive polysilicon layer and a dielectric layer composed of a silicon oxide layer interposed between the first electrode layer and the second electrode layer. The respective capacitor subunits are connected in parallel to each other through a connector.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: Methods are provided for forming a transistor for use in an active matrix liquid crystal display (AMLCD). In one aspect a method is provided for processing a substrate including providing a glass substrate, depositing a conductive seed layer on a surface of the glass substrate, depositing a resist material on the conductive seed layer, patterning the resist layer to expose portions of the conductive seed layer, and depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique.

Abstract: In a method for forming a semiconductor device, the major surface of a substrate is separated into a first element region for forming a first field-effect transistor and a second element region for forming a second field-effect transistor. A silicon nitride film is formed in each of the first and second element regions. Thereafter, the silicon nitride film formed in the second element region is removed, and the substrate is subjected to heat treatment in an ambient that contains nitrogen oxide. Thereby, the silicon nitride film in the first element region is oxidized to form an oxynitride film, and a silicon oxynitride film is formed in the second element region. Thereafter, a high-dielectric-constant film is formed on the silicon oxynitride films in each of the first and second element regions.

Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: A method of manufacturing a flash memory device, in which a spike annealing is performed after an ion implantation for controlling a threshold voltage. Therefore, it is possible to obtain a uniform and stabilized doping profile for controlling a threshold voltage, to use BF2 ions as a dose for controlling a threshold voltage to obtain a shallow channel junction, to obtain different doping profiles in the channel junction depending on the process conditions and the atmosphere in the spike annealing equipment, and to control a doping profile for controlling a threshold voltage.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate electrode; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and including a pair of ohmic contact areas doped with conductive impurity; source and drain electrodes formed on the ohmic contact areas at least in part; a passivation layer formed on the source and the drain electrodes and having a contact hole exposing the drain electrode at least in part; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.

Abstract: A method of oxidizing work pieces according to the present invention comprises the steps of: containing a plurality of work pieces W in a processing vessel 22 which has a predetermined length and is capable forming a vacuum therein, oxidizing surfaces of the work pieces in an atmosphere including active oxygen species and active hydroxyl species which are generated by supplying an oxidative gas and a reductive gas into the processing vessel to interact the gases. The oxidative gas and the reductive gas are respectively supplied into the processing vessel in the longitudinal direction. Parts of the reductive gas are additionally supplied from at least two or more independently controlled gas nozzles located at separate locations in the longitudinal direction of the processing vessel. The gas flow rate through each nozzle is set depending on any combination of the work pieces composed of product wafers, dummy wafers, and monitor wafers in the processing vessel.

Abstract: The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.

Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.

Abstract: A method of reducing trench aspect ratio. A trench is formed in a substrate. Using HDP-CVD, a conformal first oxide layer is formed on a surface of the trench. A conformal first nitride layer is formed on the first oxide layer. Part of the first nitride layer is removed to cause the first nitride layer to be lower than a top surface of the substrate. Using a BOE solution, the first nitride layer and part of the first oxide layer are removed to leave a remaining first oxide layer on the lower portion of the surface of the trench. Thus, the trench aspect ratio is reduced.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: An optical semiconductor module having a large endothermic amount of an electronic cooling element can be provided, even if the area of the bottom plate of a package is the same. A package 11 includes two or more units of electronic cooling element 16 mounted therein. Each unit of the electronic cooling element is inserted through the space between inner juts 14a of ceramic feedthrough of the package 11 and a bottom plate 13, and is fixed to the bottom plate. The plural units of electronic cooling element are connected in series by one or more copper piece. The total area of junction between the two or more units of electronic cooling element and the bottom plate area of the package 11 occupies 75% or more of the area of the bottom plate. Thus, the ratio of the area of junction between the bottom plate and the electronic cooling element as a whole to the area of the bottom plate of the package can be increased.

Abstract: A semiconductor package assembly is disclosed having a semiconductor die receiving member configured to accept a semiconductor die in either the flip-chip or the wirebond orientations. First contact sites on a die receiving surface provide electrical connection with a flip-chip component. Second contact sites provide electrical connection with a wirebond component. Electrically conductive traces connect the first and second contact sites with terminal contact sites. The semiconductor package assembly may further include the flip-chip or wirebond component mounted over the die receiving surface. Further, the assembly may also include a mounting substrate in electrical connection with the terminal contact sites.

Abstract: A process for selective deposition of material on electrodes of chips made from a single substrate. The process includes forming a plurality of chips on the same substrate. Each chip includes a plurality of electrodes, address pads, and an address area containing the programmed address of the chip. The address areas are connected to the address pads and capable of recognizing the address of the chip to activate the chip. The process also includes establishing electrical connections to connect the address pads and the plurality of electrodes on each chip for the activation of the chips and polarization of the electrodes. Further, the process includes addressing the chips and electrodes on which a first material is to be deposited, and simultaneously depositing the first material on the addressed electrodes of the activated chips. The addressing and deposition steps are repeated as many times as necessary to make material depositions on the other electrodes.

Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.

Abstract: A device manufacturing method capable of imaging structures on both sides of a substrate, is presented herein. One embodiment of the present invention comprises a device manufacturing method that etches reversed alignment markers on a first side of a substrate to a depth of 10 ?m, the substrate is flipped over, and bonded to a carrier wafer and then lapped or ground to a thickness of 10 ?m to reveal the reversed alignment markers as normal alignment markers. The reversed alignment markers may comprise normal alignment patterns overlaid with mirror imaged alignment patterns.

Abstract: The present invention relates to a fabrication method of nitride-based semiconductors and a nitride-based semiconductor fabricated thereby. In the fabrication method of the invention, a self-organizing metal layer is formed on a sapphire substrate. The sapphire substrate having the self-organizing metal layer is heated so that self-organizing metal coalesces into nanoscale clusters to irregularly expose an upper surface of the sapphire substrate. Exposed portions of the sapphire substrate is plasma etched using the self-organized metal clusters as a mask to form a nanoscale uneven structure on the sapphire substrate. A resultant structure is wet etched to remove the self-organized metal clusters. The nanoscale uneven structure formed on the sapphire substrate decreases the stress and resultant dislocation between the sapphire substrate and a nitride-based semiconductor layer as well as increases the quantum efficiency between the same.