Abstract: A method for producing a semiconductor device of the present invention includes forming a surface electrode on a semiconductor element, forming a solder layer by plating on one principal surface of the surface electrode, mounting the semiconductor element on the sub-mount so that the solder layer contacts a principal surface of the sub-mount, and bonding the sub-mount and the semiconductor element to each other via the solder layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches.

Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

Abstract: The invention relates to wavelength-selective and tunable optical filters for transmitting the light in a narrow optical spectral band, centered around an adjustable wavelength, and for blocking the transmission of wavelengths lying outside of this band. In a micromachined monolithic structure containing the optical filter proper, the component comprises a low-absorption light detection element used for slaving the tuning control of the filter to a wavelength received by the filter, this element transmitting the majority of the radiation at this wavelength. The filter is a Fabry-Pérot interferometric filter, the cavity (C) of which is tuned to a value that maximizes the power detected by the light detection element. The filter is preferably based on layers of indium phosphide and air gaps. The detection element preferably comprises a layer of gallium-indium arsenide 74 suitable for detection of the intended wavelength band.

Abstract: According to the present invention, a substrate 11, a cluster of LED chips, which are arranged two-dimensionally on the substrate 11, and a plurality of phosphor resin portions 13a, 13b that cover the respective LED chips are provided. The phosphor resin portion 13a, 13b includes a phosphor for transforming the emission of its associated LED chip into a light ray having a longer wavelength than that of the emission. A size of the phosphor resin portions 13b, which cover the LED chips located in an outer region of the cluster, is set bigger than that of the other phosphor resin portions 13a, which cover the LED chips located in the remaining non-outer region.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: A solid-state image sensor includes, in each pixel, a p-type well provided on a semiconductor substrate, a photodiode provided in the p-type well, a transfer gate for transferring photocharges accumulated in the photodiode, and an n-type diffusion region for receiving the transferred photocharges. The photodiode includes a first n-type accumulation region, and a second n-type accumulation region having a concentration higher than that of the first accumulation region and provided at a position deeper than the first accumulation region. The first accumulation region extends toward an end of the transfer gate, and the second accumulation region is separate from the transfer gate.

Abstract: The invention is to suppress a leak current in a photodiode and an unevenness in the leak currents. In a photoelectric converting device including a channel stop area of a higher concentration than in an element isolating insulation film formed between a photodiode, having an n-type semiconductor area formed in a p-type semiconductor, and an adjacent element, and in a p-type semiconductor layer formed under the element isolating insulation film, and a wiring layer formed in a part on the element isolating insulation film, the wiring layers on the element isolating insulation film adjacent to the photodiodes are unified in an effective area and a potential, and a p-type dark current reducing area of a higher concentration than in the channel stop area is provided in at least a part of an area opposed to the wiring layer across the element isolating insulation film.

Abstract: A semiconductor integrated circuit device has a first MOS transistor and a second MOS transistor. The first MOS transistor has a first source, a first gate electrode, and a first wiring metal connected to the first source and overlapping the first gate electrode. The second MOS transistor has a second source, a second gate electrode, and a second wiring metal connected to the second source. The first wiring metal of the first MOS transistor and the second wiring metal are positioned so that they do not overlap the second gate electrode.

Abstract: In the preferred embodiment, a thick regular-k dielectric is formed on a substrate. A tungsten plug is formed in the thick regular-k dielectric. The thick regular-k dielectric is recessed and a thin low-k dielectric is formed on the thick regular-k dielectric. The thin low-k dielectric acts as a glue layer and as an etch stop layer. A thick low-k dielectric is formed on the thin low-k material. Optionally, an opening is formed through the thick low-k dielectric to expose the tungsten plug. The opening is then filled with copper or copper alloys.

Abstract: A liquid crystal display panel including a thin film transistor array substrate structure including, a substrate, a gate line and a data line disposed on the substrate and insulated from each other by a gate insulating pattern, a thin film transistor provided at intersection of the gate and data lines, a protective film disposed to protect the thin film transistor, and a pad structure connected to a respective one of the gate line and data line, the pad structure including a transparent conductive film and a data metal layer; and a color filter array substrate structure joined with the thin film transistor array substrate structure, wherein the protective film is disposed within an area where the color filter array substrate structure overlaps with the thin film transistor array substrate structure, and exposing either the data metal layer or the transparent conductive film along a side portion of the substrate.

Abstract: A divided drain implant structure for transistors used for electrostatic discharge protection is disclosed. At least two transistors are formed close to each other on a substrate with their gates and sources coupled together and with the drains placed next to each other and separated as a divided drain implant structure. The divided drain implant structure further comprises at least two drain implant regions separated by a lightly doped drain region and a halo implant region formed underneath. At least one of the drain implant regions is coupled to an input/output pad of a circuit.

Abstract: The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and microelectronic component packages. In one particular example, a microelectronic component package includes a substrate and a microelectronic component that has a first surface with a surface area greater than that of a second surface. A cementitious material, e.g., a die attach paste, may attach the second surface of the microelectronic component to a mounting surface of the substrate, with the cementitious material extending outwardly beyond a perimeter of the second surface and covering a surface area of the mounting surface that is no greater than the surface area of the first surface. Such a microelectronic component package may be formed with a smaller footprint or, alternatively, may include a microelectronic component having larger dimensions in a microelectronic component package of the same size.

Abstract: The invention reduces the resistance of a feed line in a display device (electro-optical device), and reduces the loss in the current supply to a light-emitting element, etc. In an electro-optical device including an electro-optical element and a driver circuit to drive the electro-optical element, a wiring board used for the electro-optical device includes a feed line film to supply the driver circuit with current to put the electro-optical element into operation; a signal line film to supply the driver circuit with a level signal to determine intensity of the current to be supplied to the electro-optical element; and an operation line film to supply the driver circuit with an operation instruction signal to instruct whether to put the electro-optical element into operation, and the feed line film constitutes an upper layer among the feed line film, the signal line film, and the operation line film.

Abstract: An electron transfer device is implemented in a structure which is readily capable of achieving charge transfer cycle frequencies in the range of several hundred MHz or more and which can be formed by conventional semiconductor integrated circuit manufacturing processes. The device includes a substrate having a horizontal extent and a pillar on the substrate extending from the substrate vertically with respect to the horizontal extent of the substrate. The pillar is formed to vibrate laterally with respect to the vertical length of the pillar at a resonant frequency which can be several hundred MHz. Drain and source electrodes extend from the substrate vertically with respect to the horizontal extent of the substrate, and have innermost ends on opposite sides of the pillar. The pillar is free to vibrate laterally back and forth between the innermost ends of the drain and source electrodes to transfer charge between the electrodes.

Abstract: The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor layout structure is described. The CMOS image sensor layout structure includes a substrate, a plurality of light sensing devices, a plurality of transistors and a plurality of color-filtering film layers. The substrate has a pixel array region comprising a plurality of pixels. Each pixel has a light sensing region and an active device region. The pixels are isolated from one another by isolation structures and the light sensing regions have different sizes. The light sensing devices are defined separately within the respective light sensing regions. The transistors are disposed within the respective active device region. The color-filtering film layers are disposed separately above the pixels to form a color-filtering array.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f