Abstract: A method of forming a semiconductor package including placing a semiconductor chip in cavities of a semiconductor chip carrier substrate.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A semiconductor arrangement is disclosed, having transistors based on organic semiconductors and non-volatile read/write memory cells. The invention relates to a semiconductor arrangement, constructed from transistors, in the case of which the semiconductor path is composed of an organic semiconductor, and memory cells based on a ferroelectric effect perferably in a polymer, for use in RF-ID tags, for example.

Abstract: In accordance with the present invention, a dielectric barrier layer is presented. A barrier layer according to the present invention includes a densified amorphous dielectric layer deposited on a substrate by pulsed-DC, substrate biased physical vapor deposition, wherein the densified amorphous dielectric layer is a barrier layer. A method of forming a barrier layer according to the present inventions includes providing a substrate and depositing a highly densified, amorphous, dielectric material over the substrate in a pulsed-dc, biased, wide target physical vapor deposition process. Further, the process can include performing a soft-metal breath treatment on the substrate. Such barrier layers can be utilized as electrical layers, optical layers, immunological layers, or tribological layers.

Abstract: A thin film transistor with a microlens. A metal gate is formed on a substrate. A gate dielectric covers the metal gate. A semiconductor layer is formed on the gate dielectric. Source/drain metal layers respectively overlap ends of the top surface of the semiconductor layer such that the semiconductor layer between the source/drain metal layers is exposed. The microlens is formed on the exposed top surface of the semiconductor layer.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conduction type; an active region used as a function-element-forming region on the semiconductor substrate; a low-resistance region of a second conduction type formed on an outermost periphery of the active region to surround the active region and having contact with the semiconductor substrate, the second conduction type being different from the first conduction type; and an electrode connected to the function element and the low-resistance region. A diode is formed by the semiconductor substrate and the low-resistance region. The function element and the diode are electrically connected in parallel between the semiconductor substrate and the electrode, and, between the semiconductor substrate and the electrode, resistance of the low-resistance region is lower than resistance of an electrical conduction path via the function element.

Abstract: An apparatus for transverse characterization of materials includes a lower pattern of contacts, separated by spacings, a material, and an upper pattern of a multiplicity of contacts, separated by spacings differing from the spacings of the lower pattern. The transverse characterization method includes receiving lower pattern of a multiplicity of contacts, separated by spacings along a surface, with a material above the surface, successively placing an upper contact near the upper surface of the material in an upper pattern of locations separated by spacings differing from the spacings of the lower pattern, measuring the characteristics between the upper contact and one or more contacts of the lower pattern and evaluating the measured characteristics to previous measurements, wherein the evaluation provides the transverse characterization.

Abstract: A semiconductor device having a termination structure, which includes at least one spiral resistor disposed within a spiral trench and connected between two power poles of the device.

Abstract: A semiconductor component, such as a humidity sensor, which has a semiconductor substrate, such as, for example, made of silicon, a first electrode and a second electrode and at least one first layer that is accessible for a medium acting from the outside on the semiconductor component, the first layer being arranged at least partially between the first and the second electrode. To reduce the costs for producing the semiconductor component the first layer has pores into which the medium reaches at least partially.

Abstract: A multiple power density packaging structure with two or more semiconductor chips on a common wiring substrate having a common thermal spreader with a planar surface in thermal contact with the non-active surfaces of the chips. The semiconductor chips have different cooling requirements and some of the chips are thinned to insure that the chips requiring the lowest thermal resistance has the thinnest layer of a thermal adhesive or metal or solder interface between the chip and thermal spreader.

Abstract: A light emitting device includes a nitride semiconductor substrate with a resistivity of 0.5 ?·cm or less, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at a first main surface side of the nitride semiconductor substrate, and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein one of the nitride semiconductor substrate and the p-type nitride semiconductor layer is mounted at the top side which emits light and the other is placed at the down side, and a single electrode is placed at the top side. Therefore, there is provided a light emitting device which has a simple configuration thereby making it easy to fabricate, can provide a high light emission efficiency for a long time period, and can be easily miniaturized.

Abstract: A differential pressure sensor has a semiconductor wafer having a top and bottom surface. The top surface of the wafer has a central active area containing piezoresistive elements. These elements are passivated and covered with a layer of silicon dioxide. Each element has a contact terminal associated therewith. The semiconductor wafer has an outer peripheral silicon frame surrounding the active area. The semiconductor wafer is bonded to a glass cover member via an anodic or electrostatic bond by bonding the outer peripheral frame to the periphery of the glass wafer. An inner silicon dioxide frame forms a compression bond with the glass wafer when the glass wafer is bonded to the silicon frame. This compression bond prevents deleterious fluids from entering the active area or destroying the silicon. The above described apparatus is mounted on a header such that through holes in the glass wafer are aligned with the header terminals.

Abstract: A method of fabricating an integrated spatial light modulator with contact structures. The method includes providing a first substrate having a bonding surface, providing a device substrate having a device surface, and depositing a first layer on the device surface, the first layer having an upper surface opposite the device surface. The method also includes patterning the first layer to define a plurality of contact structure openings, depositing a conductive layer on the upper surface of the first layer, reducing the thickness of the conductive layer, and removing at least a portion of the first layer to expose a plurality of contact structures. The method further includes depositing a standoff layer on the first layer, forming standoff structures from the standoff layer, and joining the bonding surface of the first substrate to the standoff structures to form a bonded substrate structure.

Abstract: Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package increases the heat transfer away from the IC chip and electronics package, thereby cooling the chip and the package.

Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.

Abstract: A semiconductor device includes a semiconductor substrate having a resistivity of at least 30 ?·cm, a first MISFET formed on the semiconductor substrate to function as a protective element, and a second MISFET protected by the first MISFET.

Abstract: An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.

Abstract: A MEMS inertial sensor is secured within a premolded-type package formed, at least in part, from a low moisture permeable molding material. Consequently, such a motion detector should be capable of being produced more economically than those using ceramic packages. To those ends, the package has at least one wall (having a low moisture permeability) extending from a leadframe to form a cavity, and an isolator (with a top surface) within the cavity. The MEMS inertial sensor has a movable structure suspended above a substrate having a bottom surface. The substrate bottom surface is secured to the isolator top surface at a contact area. In illustrative embodiments, the contact area is less than the surface area of the bottom surface of the substrate. Accordingly, the isolator forms a space between at least a portion of the bottom substrate surface and the package. This space thus is free of the isolator.

Abstract: A composite film comprised of three layers is formed by ALD on a substrate with a substrate interface surface. A first layer is coupled to the substrate interface surface. The first layer provides adhesion to the substrate interface surface and initiation of layer by layer ALD growth. A second layer is positioned between the first and third layers and provides a conducting diffusion barrier between the substrate and subsequent overlaying film. A third layer has a surface that is configured to provide adhesion and a texture template in preparation for a subsequent overlaying film. The composite engineered barrier structures are applied to interconnect, capacitor and transistor applications.

Abstract: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.