Abstract: Disclosed in an embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a reflective layer disposed on the second electrode and including a first metal; and a nitride of the first metal between the second electrode and the reflective layer.

Abstract: Disclosed herein are organic photosensitive optoelectronic devices comprising two electrodes in superposed relation; a mixed photoactive layer located between the two electrodes, wherein the mixed photoactive layer comprises at least one donor material having a HOMO energy and at least one acceptor material having a LUMO energy, wherein the at least one donor material and the at least one acceptor material form a mixed donor-acceptor heterojunction; a photoactive layer adjacent to and interfacing with the mixed photoactive layer, wherein the photoactive layer comprises a material having a LUMO energy within 0.3 eV of the LUMO energy of the at least one acceptor material or a HOMO energy within 0.3 eV of the HOMO energy of the at least one donor material; and a buffer layer adjacent to and interfacing with the mixed photoactive layer.

Abstract: Provided are a magnetic tunnel junction device and a method of fabricating the same. The magnetic tunnel junction device includes a heavy metal layer, a free magnetic layer disposed on the heavy metal layer, and a tunnel insulating layer disposed on the free magnetic layer. The heavy metal layer includes platinum (Pt), the free magnetic layer includes cobalt (Co), a magnetization state of the free magnetic layer has an easy-cone state, the free magnetic layer has a positive first-order perpendicular magnetic anisotropy constant and a negative second-order perpendicular magnetic anisotropy constant, and the tunnel insulating layer includes magnesium oxide (MgO).

Abstract: The present invention relates to an organic radiation-emitting component with an active organic layer constituted to generate radiation and one or two radiation-output sides, characterised in that, on at least one radiation-output side of the component, a UV protective film is arranged and connected to the component, wherein the UV protective film contains at least one first layer (A) and a second layer (B), wherein the first layer (A) contains 0.01 to 20% by weight, with reference to the total weight of the first layer (A), of a UV absorber, and wherein the second layer (B) contains polycarbonate. Furthermore, the invention relates to the use of a component according to the invention as an organic light-emitting diode, and for lighting, especially for general lighting.

Abstract: LDMOS device including a drift region, a body region, a gate dielectric layer, a polysilicon gate, a source region, a drain region and a common dielectric layer, the common dielectric layer covers a portion, between a second side of the polysilicon gate and the drain region, of the surface of the drift region, extends onto the surface of the polysilicon gate and also covers part of the surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves as a growth barrier layer of the self-aligned metal silicide; a drain terminal field plate is formed on a portion of the surface of the common dielectric layer; and a portion of the common dielectric layer serves as a field plate dielectric layer.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: The present disclosure is directed to systems and methods for automatically calibrating a load sensor system of a wind turbine and determining health of same. In one embodiment, the method includes receiving a plurality of sensor signals generated by the plurality of load sensors from the load sensor system. The method also includes determining, via a computer model, a load estimation of the wind turbine based on the sensor signals, turbine geometry, and one or more additional input parameters (e.g. rotor azimuth angle, pitch angle, rotor position, etc.). Another step includes comparing the load estimation to a load measurement to determine one or more correlation coefficients. Thus, the method also includes calibrating the plurality of sensors in the load sensor system based on the correlation coefficients.

Abstract: Provided is a display device including a substrate including a display area and a non-display area; a thin-film transistor and a display element on the display area; an organic insulating layer between the thin-film transistor and the display element; a first power supply voltage line arranged to correspond to one side of the display area in the non-display area; a second power supply voltage line spaced apart from the first power supply voltage line; and an inorganic protective layer that covers at least a portion of the second power supply voltage line. The second power supply voltage line includes a first region and a second region. The first region has a stack of a first conductive layer, a second conductive layer, and the organic insulating layer. The second region has a stack of the first conductive layer and the inorganic protective layer.

Abstract: A storage device includes a first conductor, a second conductor, a variable resistance layer, a first portion, and a second portion. The variable resistance layer connects with the first conductor or the second conductor. The first portion is provided between the first conductor and the second conductor, and has a first threshold voltage value at which the resistance value changes. The second portion is provided between the first conductor and the first portion and/or between the second conductor and the first portion, and has a second threshold voltage value at which the resistance value changes and which is higher than the first threshold voltage value.

Abstract: A system for rapidly adapting production of a product based on classification of production data using a classifier trained on prior production data is provided. A production control system includes a learning system and an adaptive system. The learning system trains a production classifier to label or classify previously collected production data. The adaptive system receives production data in real time and classifies the production data in real time using the production classifier. If the classification indicates a problem with the manufacturing of the product, the adaptive system controls the manufacturing to rectify the problem by taking some corrective action. The production classifier is trained using bootstrap data and corresponding example data extracted from prior production data. Once the bootstrap data is labeled, the corresponding example data is automatically labeled for use as training data.

Abstract: A method includes forming a dummy gate structure over a substrate, forming a plurality of gate spacers respectively on opposite sidewalls of the dummy gate structure and having a first dielectric constant, removing the dummy gate structure to form a gate trench between the gate spacers, forming a dopant source layer to line the gate trench, annealing the dopant source layer to diffuse k-value reduction impurities from the dopant source layer into the gate spacers to lower the first dielectric constant of the gate spacers to a second dielectric constant, and forming a replacement gate stack in the gate trench.

Abstract: The present disclosure relates to an array substrate, manufacturing method thereof and display device using the same. The method for manufacturing the array substrate includes: forming an amorphous silicon layer and an insulating layer covering the amorphous silicon layer in one deposition process; and processing the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer. Through the above-mentioned method, the present disclosure can solve the problem of affecting the concentration of current carriers that caused by the oxidation of the surface of polysilicon, and improve the performance of the array substrate.

Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.

Abstract: A semiconductor structure is provided. A non-limiting example of the structure includes a substrate and a plurality of first pillars of a conductive material above a first portion of the substrate. The structure further includes a plurality of second pillars of the conductive material above a second portion of the substrate, wherein the plurality of first pillars are offset by a gap distance from the plurality of second pillars along a longitudinal axis.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.

Abstract: An optoelectronic semiconductor structure includes a first n-type semiconductor layer, a first quantum well layer, a first p-type semiconductor layer, and a second n-type semiconductor layer. The first quantum well layer is disposed on the first n-type semiconductor layer. The first p-type semiconductor layer is disposed on the first quantum well layer. The second n-type semiconductor layer is disposed on the first p-type semiconductor layer. The second n-type semiconductor layer includes both an n-type dopant and a p-type dopant. The concentration of the n-type dopant in the second n-type semiconductor layer is greater than the concentration of the p-type dopant in the second n-type semiconductor layer. The first n-type semiconductor layer, the first quantum well layer, the first p-type semiconductor layer, and the second n-type semiconductor layer form a bipolar phototransistor structure. A manufacturing method of the optoelectronic semiconductor structure is also provided.

Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a plurality of wiring layers stacked via a plurality of insulating layers above the substrate, the wiring layers having an opening extending in a direction perpendicular to the substrate, each of the wiring layers including a first face recessed in a first direction, a second face recessed in a second direction, third face recessed in a third direction, and a fourth face recessed in a fourth direction; a block insulating film provided to be in contact with each of the first to fourth faces; a charge storage film provided on a side face of the block insulating film; a tunnel insulating film provided on a side face of the charge storage film; and a semiconductor film provided on a side face of the tunnel insulating film.

Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.