Abstract: A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.

Abstract: During the process in which a metal strip is moved in a floating condition, the metal strip is first heated, and thereafter cooled and annealed. In heating the metal strip, the metal strip is heated so that a central portion widthwise thereof is increased in temperature more than that of both edges widthwise thereof. The metal strip is heated in a manner as described whereby a great thermal stress is not introduced in the metal strip and consequently, there is less possibility to produce wrinkles in the metal strip.

Abstract: A method of manufacturing a semiconductor device is provided in which a masking layer is formed on a part of a surface of a monocrystalline semiconductor body and the semiconductor body is then subjected at the side of the surface to an epitaxial treatment from a gaseous phase, and an epitaxial layer is deposited of which a portion on the uncovered part of the surface is monocrystalline and a portion on the masking layer is polycrystalline. This method is characterized in that, prior to the epitaxial treatment, an amorphous or polycrystalline layer is deposited both on the masking layer and on the uncovered part of the surface at a temperature which is lower than that at which the epitaxial layer is deposited. In this layer the layer portion on the uncovered surface part changes into the monocrystalline state by a thermal treatment preceding the deposition of the epitaxial layer.

Abstract: A bipolar transistor process and device wherein the transistor is fabricated within a laterally isolated device region, into which is formed a lateral intradevice isolation groove prior to formation of device/active and contact regions. The lateral intradevice isolation groove with the lateral device isolation assists in self-alignment of device regions. The lateral intradevice isolation permits the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate and facilitates extremely close spacing of active regions at the planar surface.

Abstract: To render severing of electrical conductors on integrated circuit (IC) chips more reliable, the region of insulating material, typically silicon oxide, beneath the zone which is to be severed, is increased in thickness; the increase in thickness is, preferably, in stepped form, so that the heat capacity at the point of severing of the conductor is less than the heat dissipation at other regions of the conductor, and especially at the point of application of the current probes. Preferably, the contact points at which the current probes are applied are located directly on the semiconductor surface without any intervening insulating oxide layer.

Abstract: A laminated conductor includes a lower thin film of nickel-X alloy or pseudo alloy deposited upon a substrate containing silicon or upon a substrate intended for use as a magnetic bubble storage device. Upon the film of nickel-X alloy, a thicker film of gold is deposited as the conductive portion of the conductor. On the upper surface of the gold layer is deposited a thin film of nickel-X alloy. Failure of the conductor because of electromigration is reduced dramatically as compared with use of molybdenum instead of nickel in the laminated structure. The nonmagnetic nickel-X alloy does not interfere with magnetic fields or produce unwanted magnetic fields.

Abstract: Impurity ions implanted into a semiconductor silicon substrate are not redistributed during a heating of the substrate from the substrate to the film. Such redistribution does not occur due to the direct nitridation of the silicon substrate for forming the silicon nitride film.

Abstract: The present invention deals with a method of taking out a substrate electrode of a LOCOS-type silicon gate MOSIC device from the surface of the semiconductor substrate. According to the present invention, a masking layer for preventing the introduction of impurities is formed on the periphery of the semiconductor substrate simultaneously with the masking step for forming a resistor of polycrystalline silicon, the mask is removed after the impurities have been introduced, and a substrate electrode is formed on the exposed surface of the semiconductor substrate.

Abstract: A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages. The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region. The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket.

Abstract: Porous silica doped with zinc is used as a p-type dopant source in the construction of rib lasers. Other modifications include allowing the zinc diffusion to go right through the active layer and to dimension the device so that lateral optical guidance is unaffected by the rib.

Abstract: An article of manufacture of a titanium reinforcing part having a grain structure to impart dimensional stability to the part at elevated temperatures is integrally joined to a titanium sheet having a grain structure to become superplastic at elevated temperatures. The completed composite titanium part is formed with the titanium sheet superplastically forming to intimately contact and to become diffusion bonded to the dimensionally stable titanium part.

Abstract: A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.

Abstract: For an integrated circuit semiconductor device having a multiplicity of MOSFET elements, voltage-invariant capacitors, each with metal as one plate and either polysilicon or source-drain diffusion as the second plate, are created by regrowing a thin oxide layer to provide the dielectric of the capacitor during the normal MOSFET processing sequence.

Abstract: Suitably modified molecular beam epitaxy (MBF) techniques are used to synthesize single crystal, periodic monolayer superlattices of semiconductor alloys on single crystal substrates maintained below a critical growth temperature. Described is the fabrication of periodic structures of (GaAs).sub.n (AlAs).sub.m, where m and n are the number of contiguous monolayers of GaAs and AlAs, respectively, in each period of the structure. As many as 10,000 monolayers were grown in a single structure. Also described is the MBE growth of (Al.sub.x Ga.sub.1-x As).sub.n (Ge.sub.2).sub.m, quasi-superlattice and non-superlattice structures depending on the particular values of n, m and the growth temperature. Waveguides, heterostructure lasers and X-ray reflectors using some of the structures are also described.

Abstract: A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions.

Abstract: An integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer. High value polysilicon resistors are formed over an outer protective silicon dioxide layer of the silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors. The process for making the integrated circuit includes forming a sheet of polysilicon over the entire wafer surface, performing the ion implantation and etching away all but the desired resistor portions of the polysilicon. It also includes heating the wafer to simultaneously anneal the ion implanted polysilicon, form the gate oxide, thicken the oxide over the emitters, and cover the resistor body with a thin protective oxide film.

Abstract: A free machining cast steel shape containing bismuth which functions as a liquid metal embrittler. The ability of the bismuth to function as a liquid metal embrittler is enhanced by restricting the total amount of ingredients which lower the wetting ability of the bismuth to less than the bismuth content and by controlling the amount of strengthening elements added to the steel.

Abstract: In a complementary pair of bipolar transistors, one vertical and one lateral, the vertical transistor includes a heavily doped buried emitter, lightly doped buried graded base and a heavily doped surface collector and the lateral transistor includes a lightly doped substrate base and heavily doped emitter and collector. The lateral transistor's collector isolates the lateral transistor's base from the vertical transistor's collector.This integrated circuit approach includes the I.sup.2 L structure of the present invention and T.sup.2 L devices. The I.sup.2 L transistors are in dielectrically isolated regions with the vertical transistors emitter being connected to the polycrystalline support through a vertical opening in the dielectric isolation.

Abstract: V-shaped lateral dielectric isolation grooves divide a semiconductor layer into a plurality of regions. The oxide layer above the polycrystalline material in the grooves is thicker than the field oxide layer on the semiconductor layer to prevent the creation of retrograde surface profiles and mask the polycrystalline material during self-aligned device fabrication in the semiconductor layer. The field oxide is formed on the semiconductor layer before the isolation groove fabrication and prevented from increasing in thickness by an oxide inhibiting layer during the isolation groove fabrication.

Abstract: A free machining cast steel shape has in its microstructure, both bismuth-containing inclusions and manganese sulfide inclusions. The manganese sulfide inclusions act as microcrack initiators, and the bismuth-containing inclusions act as liquid metal embrittlers, propagating the microcracks. The mean size and spacing of the manganese-sulfide inclusions are controlled.