Abstract: A process is described which combine polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Abstract: A lateral PNP transistor is formed by diffusing N type inpurities into an N type layer to form base contact region and base region, diffusing P type impurities into the N base region and N layer to form emitter and collector regions respectively, and counter doping the layer area between the N base region and the collector region. The counter doping is performed through a non-critical mask aperture extending between the emitter and collector regions.

Abstract: A variable temperature method for the preparation of single and multiple epitaxial layers of single-phase (e.g., face-centered cubic), ternary lead chalcogenide alloys (e.g., lead cadmium sulfide, [Pb.sub.1-w Cd.sub.w ].sub.a [S].sub.1-a wherein w varies between zero and fifteen hundredths, inclusive, and a=0.500.+-.0.003), deposited upon substrates of barium fluoride, BaF.sub.2, maintained in near thermodynamic equilibrium with concurrently sublimated lead alloy and chalcogenide sources. During preparation, the temperature of the substrate is varied, thereby providing an epilayer with graded composition and predetermined electrical and optical properties along the direction of growth. This growth technique can be used to produce infrared lenses, narrowband detectors, and double heterojunction lasers.

Abstract: Method of fabricating monolithic integrated circuit structure incorporating a full-wave diode bridge rectifier of four Schottky diodes. A body of silicon is produced by growing an epitaxial layer of N-type silicon on a P-type substrate. P-type imparting material is diffused into the layer to form isolating barriers delineating first and second N-type zones separated from each other by intervening P-type material and third and fourth N-type zones which are contiguous. A mixture of titanium and tungsten is deposited on portions of the zones and heated to form a mixed silicide. Schottky rectifying barriers are produced at the interfaces of the mixed silicide and N-type zones.

Abstract: An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Abstract: A semiconductor device is manufactured by covering a semiconductor substrate of a predetermined conductivity type with a polycrystal layer of a semiconductor material. Selected portions of the polycrystal layer are oxidized into an insulating material during heat treatment. Remaining portions of the polycrystal layer which are left unoxidized act as conductive portions. On manufacturing a bipolar transistor, ion implantation is carried out in a predetermined solid angle to introduce an impurity of an opposite conductivity selectively in a preselected one of the remaining portions. During the heat treatment, the impurity diffuses into the substrate only from the preselected portion to form a PN junction in the substrate. For fabricating an MOS transistor, an oxide film is preliminarily formed on the substrate selectively on an area on which a predetermined one of the remaining polycrystal layer portions is to be formed.

Abstract: A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are disclosed for forming an abrupt and accurately positioned p-n junction between a substrate and a substrate-adjoining region. This is achieved in accordance with the present invention by diffusing zinc or cadmium from a surface of the substrate-adjoining region to the substrate, and abruptly limiting or retarding the diffusion of the zinc or cadmium into the substrate near a junction between the substrate and the region. This is accomplished in accordance with the present invention by selecting the net donor concentration in the substrate near the junction to be higher than the concentration of zinc or cadmium at the surface of the substrate-adjoining region.

Abstract: A method for producing doped gallium arsenide semiconductor layers for semiconductor devices wherein a predetermined flow of a reactive substance is directed over a material having a dopant and a relatively low vapor pressure. The reactive substance chemically reacts with the material to produce a corresponding flow of a doping vapor. The doped gallium arsenide semiconductor layer is deposited on a gallium arsenide substrate by vapor phase epitaxy from material including the doping vapor. With such method, accurate control of the magnitude of the dopant is obtained by control of the reactive substance, the doping material being supplied by a non-volatile source.

Abstract: A method for manufacturing a npn-type transistor includes steps of depositing phosphorus on a base region, covering the deposited phosphorus with a polycrystalline silicon layer and heating the deposited phosphorus to diffuse it into the base region to form an emitter region.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: A novel process is described for forming a gate member for an SOS device wherein the objectionable point that appears at the top of the silicon island is removed. The point results when an anisotropic etch is utilized to form the island. The process includes first forming a relatively thick layer of CVD oxide around sides at the base portion of the island while the remainder of the sides of the island, including the objectionable point, remain exposed for further processing in order to remove the point. The point is then heavily oxidized to form a bird beak which bird beak joins the gate oxide with the CVD oxide to produce a rounded edge.

Abstract: A metal-semiconductor field-effect transistor is formed by providing a blanket layer of the same conductivity type as the semiconductor body, with field oxide subsequently being grown, and with a region of opposite conductivity type being formed to extend partially under the field oxide, the initial blanket layer acting as the field implant region of the field-effect transistor.

Abstract: A method for fabricating a complementary MOS device, applicable to either silicon-on-sapphire or bulk silicon, is described wherein a buried contact is formed that is comprised of a region of doped silicon, a layer of MoSi.sub.2, a thin layer of Mo and a layer of doped polycrystalline silicon.

Abstract: A vertical pair of complementary, bipolar transistors is disclosed which includes a semiconductor substrate of one conductivity type and a pair of dielectric isolation regions disposed in contiguous relationship with the substrate. An injector region of opposite conductivity type is disposed between the pair of isolation regions. A pair of heavily doped, polycrystalline, semiconductor regions of the one conductivity type is disposed over and in registry with the pair of isolation regions. Similarly, a single crystal, semiconductor region of the one conductivity type is disposed over and in registry with the injector region. Finally, a first zone of opposite conductivity type is disposed in the single crystal region and a second zone of the one conductivity type is disposed in the first zone.

Abstract: An infrared (IR) detector device comprised of a solid state, radiation ha and high resolution monolithic IR focal plane array for imaging applications. The monolithic IR focal plane array has a heterostructure injection scheme that prevents charged-coupled device (CCD) "well filling" by using a heterojunction barrier between the absorber, or detector layer, and the transfer layer. Injection of signal charge into a CCD multiplexer is controlled by establishing a punch through condition between the absorber layer and the CCD channel. The detector layer and the CCD multiplexer are on different planes of the focal plane array.

Abstract: Solar cells are fabricated by spraying a dopant coating onto a semiconductor wafer and heating the surface of the wafer using unipolar microwaves. The resultant controlled heating drives dopant atoms from the coating into the wafer to produce a shallow junction at a selectable depth. Advantageously, metallic conductors are predeposited atop the dopant coating and then sintered to the semiconductor by the same unipolar microwave field concurrently with dopant drive-in. Efficient solar cells can be made with this process using polycrystalline silicon, since with unipolar microwave surface heating the grain boundaries do not become so deeply doped as to short circuit the junctions formed in the individual grains. Unipolar microwave heating also may be used to anneal ion implanted semiconductor devices.

Abstract: The method entails laying out NPN transistors in a bipolar integrated circuit in a manner which prevents crystal dislocations from making the transistor unreliable. The long edges of the collector contacts are aligned in a direction substantially perpendicular to the direction between the collector contact and the emitter-base junction.

Abstract: Semiconductor devices using chemically treated n-type GaAs have greatly reduced surface recombination velocities. A preferred embodiment uses fractional monolayers of ruthenium on the GaAs surface.

Abstract: A method of fabricating light emitting diodes to prevent degradation caused y thermally induced stress. A voltage is applied across the chip to cause it to bend to a prestressed condition while it is being soldered to the header. The biasing voltage applied is continued until after the heat is removed and the solder cooled leaving the diode in the prestressed condition.