Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).

Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.

Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.

Abstract: In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto.

Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract: A power semiconductor component (1) contains a weakly doped drift zone (9), a drain zone (10) and a MOS structure (12) situated at the front side (2) of the power semiconductor component (1). An edge plate (6) of the first conductivity type is provided at its edge (8) above the drift zone (9). The edge plate (6) is doped more highly than the drift zone (9). Situated above the edge plate (6) is an insulation layer (24) with an overlying field plate (7) made of polysilicon. The field plate (7) forms together with the edge plate (6) a plate capacitor structure which increases the drain-source output capacitance of the power semiconductor component (1), so that fewer radiofrequency interference disturbances are caused by the power semiconductor component (1) during switching.

Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.

Abstract: A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.

Abstract: An organic light-emitting display device includes a substrate, a first buffer layer and a second buffer layer on the substrate, a thin film transistor on the second buffer layer, an organic light-emitting diode electrically connected with the thin film transistor, and a photo sensor with an intrinsic region on the second buffer layer, wherein the photo sensor is capable of absorbing red light from the organic light-emitting diode and of exhibiting quantum efficiency of from about 50% to about 90%.

Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.

Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.

Abstract: Disclosed herein is a light-emitting device comprising a transparent or semi-transparent first substrate, a second substrate provided opposite to the first substrate, a transparent or semi-transparent first electrode provided on the first substrate, a second electrode provided on the second substrate so as to be opposite to the first electrode, and a light-emitting layer which contains a metal oxide semiconductor porous body, by the surface of which an organic light-emitting material is supported, and is provided between the first electrode and the second electrode.

Abstract: The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.

Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.

Abstract: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.

Abstract: An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Abstract: Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations (16, 19) interconnecting each of the two corresponding doped zones (4, 5; 6, 7) of the integrated circuit, to reduce the base resistances (RP?, RP?) of the two bipolar transistors, at least one of the metallizations (16, 19) performed to reduce the base resistances (RN?, RP?) of the two bipolar transistors, being connected to a power supply metallization (15, 16) in the integrated circuit, entirely through the substrate (1, 2).

Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.

Abstract: A method and system for stacking integrated circuits is described. An integrated circuit stack is formed by stacking integrated circuit pairs. The integrated circuit pairs are formed by connecting an active surface of a first integrated circuit to an active surface of a second integrated circuit using flip chip bonding. The first integrated circuit pair is connected to a substrate using an adhesive. The other integrated circuit pairs are stacked sequentially on the first integrated circuit pair using an adhesive. Wire bonding is used to connect the second integrated circuit in each of the integrated circuit pairs to the substrate.