Patents Examined by Wael M. Fahmy
  • Patent number: 7863666
    Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: January 4, 2011
    Assignee: Via Technologies, Inc.
    Inventor: Chih-Min Liu
  • Patent number: 7863126
    Abstract: A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dae-Gyu Park, Michael P. Chudzik, Vijay Narayanan, Vamsi Paruchuri
  • Patent number: 7863720
    Abstract: A method and system for stacking integrated circuits is described. An integrated circuit stack is formed by stacking integrated circuit pairs. The integrated circuit pairs are formed by connecting an active surface of a first integrated circuit to an active surface of a second integrated circuit using flip chip bonding. The first integrated circuit pair is connected to a substrate using an adhesive. The other integrated circuit pairs are stacked sequentially on the first integrated circuit pair using an adhesive. Wire bonding is used to connect the second integrated circuit in each of the integrated circuit pairs to the substrate.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: January 4, 2011
    Assignee: Honeywell International Inc.
    Inventors: Ronald J. Jensen, Richard K. Spielberger
  • Patent number: 7863611
    Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 4, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Katsumi Abe, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7863659
    Abstract: A MOS type solid-state image pickup apparatus comprises: a semiconductor substrate having a light receiving surface; a plurality of photoelectric conversion elements arranged in an array manner on the light receiving surface; a plurality of layers of wirings that goes across the light receiving surface and are stacked above the semiconductor substrate, the wirings being connected to signal reading circuits each of which is provided in association with each of the photoelectric conversion elements; and an insulation layer interposed with the layers of wirings, wherein a first wiring, which connects to a gate of a MOS transistor forming a part of each of the signal reading circuits, is provided in a lower one of the layers of wirings, and a second wiring, which connects to a source or drain of the MOS transistor, is provided in an upper one of the layers of wirings.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: January 4, 2011
    Assignee: Fujifilm Corporation
    Inventor: Makoto Shizukuishi
  • Patent number: 7863751
    Abstract: A semiconductor integrated circuit device includes: a semiconductor substrate, on which diffusion layers are formed; and multilayered wirings stacked above the semiconductor substrate to be connected to the diffusion layers via contact plugs, wherein a first wring and a second wiring formed thereabove are connected to the diffusion layers via first contact plug(s) and second contact plugs, respectively, and the number of the second contact plugs arrayed in parallel is set to be greater than that of the first contact plug(s).
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoru Takase
  • Patent number: 7858477
    Abstract: A method for manufacturing a semiconductor device includes forming a bulb-type trench separated from a surrounding gate and forming a buried bit line in the bulb-type trench, thereby preventing electric short of a word line and the buried bit line. A semiconductor device includes a vertical pillar formed over a semiconductor substrate, a surrounding gate formed outside the vertical pillar, and a buried bit line separated from the surrounding gate.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: December 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Han Nae Kim
  • Patent number: 7859001
    Abstract: A semiconductor light emitting apparatus can include a housing filled with a wavelength conversion material-containing resin material which seals a semiconductor light emitting device inside the recess of the housing. A transparent resin material can be charged on the wavelength conversion material-containing resin material, and can be configured to prevent the resin materials from being detached from each other or from other portions, such as a housing. Furthermore, such a semiconductor light emitting apparatus can emit light with less color unevenness. The housing can include a first recessed portion and a second recessed portion. The second recessed portion can have a larger diameter than the first recessed portion so as to form a stepped area at the boundary therebetween. The first recessed portion is filled with the wavelength conversion material-containing resin material as a first resin.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: December 28, 2010
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Wakako Niino, Masami Kumei, Toshimi Kamikawa, Takashi Ebisutani
  • Patent number: 7858983
    Abstract: An electrochromic display is disclosed which comprises an array-side substrate (10) wherein a TFT (14) and a pixel electrode (15) connected with the TFT (14) are formed, a color filter-side substrate (50) wherein a counter electrode (53) is formed, and an electrolyte layer (80) injected between the array-side substrate (10) and the color filter-side substrate (50). In this electrochromic display, the TFT (14) is formed to have an area not less than 30% of the area of the pixel, thereby supplying a larger current. Consequently, oxidation-reduction reaction in the electrochromic phenomenon proceeds at a higher rate, thereby enabling a high-speed response.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: December 28, 2010
    Inventors: Satoshi Morita, Takao Yamauchi, Yutaka Sano
  • Patent number: 7858994
    Abstract: An electronically active sheet includes a bottom substrate having a bottom electrically conductive surface. A top substrate having a top electrically conductive surface is disposed facing the bottom electrically conductive surface. An electrical insulator separates the bottom electrically conductive surface from the top electrically conductive surface. At least one bare die electronic element is provided having a top conductive side and a bottom conductive side. Each bare die electronic element is disposed so that the top conductive side is in electrical communication with the top electrically conductive surface and so that the bottom conductive side is in electrical communication with the bottom electrically conductive surface.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 28, 2010
    Assignee: Articulated Technologies, LLC
    Inventor: John J. Daniels
  • Patent number: 7858454
    Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 28, 2010
    Assignee: RF Nano Corporation
    Inventor: Amol M. Kalburge
  • Patent number: 7859073
    Abstract: The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Yusuke Kohyama
  • Patent number: 7855428
    Abstract: The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: December 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Mark C. Hakey, David V. Horak, Sanjay Mehta
  • Patent number: 7855146
    Abstract: A method for forming a transistor gate includes performing a first exposure of a photo-resist material on a semiconductor device. The first exposure defines a line pattern in the photo-resist material. The method also includes performing a second exposure of the photo-resist material, where the second exposure trims a resist profile of the line pattern. The method further includes etching a conductive material on the semiconductor device to form a transistor gate based on the line pattern. The first exposure could represent a best focus exposure of the photo-resist material, and the second exposure could represent a positive focus exposure of the photo-resist material. The trimming of the line pattern's resist profile may cause the transistor gate to have at least one of a rounded edge and a rounded corner. This may allow a thicker insulating material, such as tetraethylorthosilicate, to be deposited around portions of the transistor gate.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: December 21, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Li-Heng Chou, Jiankang Bu
  • Patent number: 7855108
    Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 21, 2010
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, Brian P. Wagner, David J. Knuteson, Michael E. Aumer, Andre Berghmans, Darren Thomson, David Kahler
  • Patent number: 7855410
    Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon
  • Patent number: 7851798
    Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: December 14, 2010
    Assignee: Micron Technology, Inc.
    Inventor: John Ladd
  • Patent number: 7851885
    Abstract: An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Deok-kee Kim, Keith Kwong Hon Wong, Chih-Chao Yang, Haining S. Yang
  • Patent number: 7846788
    Abstract: A method includes the steps of: introducing insulation film into a trench to provide a trench isolation; planarizing the trench isolation to expose a passivation film; and removing the passivation film and depositing a second silicon layer on a first silicon layer and the trench isolation; and in the step of depositing the first silicon layer the first silicon layer is an undoped silicon layer and in the step of depositing the second silicon layer the second silicon layer is a doped silicon layer or an undoped silicon layer subsequently having an impurity introduced thereinto or the like and thermally diffused through subsequent thermal hysteresis into the first silicon layer.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: December 7, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuki Morino, Yoshihiko Kusakabe, Ryuichi Wakahara
  • Patent number: 7846777
    Abstract: A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sang Chul Kim