Abstract: This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.

Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.

Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A nitride semiconductor device includes: a substrate having a principal surface; a first nitride semiconductor layer formed on the principal surface of the substrate and includes one or more convex portions whose side surfaces are vertical to the principal surface; and a second nitride semiconductor layer selectively grown on the side surfaces of the one or more convex portions of the first nitride semiconductor layer.

Abstract: An insulated gate semiconductor device includes a one conductivity type semiconductor layer, a first operation part in a surface of the semiconductor layer and a second operation part in the surface of the semiconductor layer that is smaller in area than the first operation part. A first channel region and a first transistor of an opposite conductivity type are provided in the first operation part and a second channel region and a second transistor of the opposite conductivity type are provided in the second operation part. The first operation part is disposed around the second operation part. Accordingly, design rules for four corner portions can be made uniform and depletion layer spreading in corner portions at a peripheral edge of a channel region of an operation part in application of a reverse voltage is also made approximately uniform. Thus, stable VDSS breakdown voltage characteristics can be obtained.

Abstract: A chip package includes a semiconductor substrate, conductive plugs and a chip. Wherein, the conductive plugs perforate the semiconductor substrate. Besides, the chip is disposed on a surface of the semiconductor substrate and electrically connected to the conductive plugs. Based on the above-described design, the chip package is capable of reducing the thermal stress problem caused by a coefficient of thermal expansion (CTE) dismatch compared with the prior art. The present invention discloses further a chip packaging process and furthermore a chip carrier and the process thereof.

Abstract: A display device including a first substrate, a first subpixel electrode, a second subpixel electrode corresponding to the first substrate, a second substrate and a common electrode formed on the second substrate is provided. The first subpixel electrode and the second subpixel electrode are formed on the first substrate. The second subpixel electrode is spaced apart from the first subpixel electrode. The common electrode has a first cutout and a second cutout. The first cutout is disposed over the first subpixel electrode and the second cutout is disposed over the second subpixel electrode. At least a portion of the first cutout has a first width and at least a portion of the second cutout has a second width different from the first width. The first width is larger than the second width in one embodiment. This structure enhances the aperture ratio and the brightness of the display device. Failures such as a residual image, stain or fingerprint may be reduced and the picture quality is improved.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.

Abstract: An optoelectronic semiconductor chip, comprising a plurality of semiconductor function regions (10) arranged on a common carrier layer (1, 7), at least one of the semiconductor function regions being a defect region (12), and a contact structure (18) for making electrical contact with the optoelectronic semiconductor chip. The contact structure is electrically conductively connected to at least one of the semiconductor function regions, and the contact structure is adapted to be electrically separated, or it is electrically separated, from the defect region.

Abstract: A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Abstract: An integrated circuit/substrate interconnect apparatus and method of manufacture are provided. Included is a substrate with a plurality of wells and a landing pad formed in each of the wells. The substrate further includes a seed layer deposited in each of the wells over the landing pad, and a metalized layer deposited in each of the wells over the seed layer. Before assembly, an upper surface of the metalized layer forms a well.

Abstract: A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first contact-making region to the second contact-making region, or vice versa. The semiconductor volume and/or the contact-making regions are configured in such a way that the local flow cross-section of a locally elevated current flow, which is caused by current splitting, is enlarged at least in partial regions of the semiconductor volume.

Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring (24), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).

Abstract: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

Abstract: An inventive semiconductor device includes at least three interconnection layers sequentially stacked without intervention of a via layer. At least one of the interconnection layers includes an interconnection and a via which connects interconnections provided in interconnection layers underlying and overlying the one interconnection layer.

Abstract: Both a compressive-stress-applying insulating film and a tensile-stress-applying insulating film cover an N-type MIS transistor formed at an SRAM access region of a semiconductor substrate. On the other hand, a tensile-stress-applying insulating film covers an N-type MIS transistor formed at an SRAM drive region of the semiconductor substrate.

Abstract: A semiconductor device has a channel termination region for using a trench 30 filled with field oxide 32 and a channel stopper ring 18 which extends from the first major surface 8 through p-well 6 along the outer edge 36 of the trench 30, under the trench and extends passed the inner edge 34 of the trench. This asymmetric channel stopper ring provides an effective termination to the channel 10 which can extend as far as the trench 30.