Patents Examined by Wael M. Fahmy
  • Patent number: 7968888
    Abstract: An object of the present invention is to provide a small solid-state image sensor which realizes significant improvement in sensitivity. The solid-state image sensor of the present invention includes a semiconductor substrate in which photoelectric conversion units are formed, a light-blocking film which is formed above the semiconductor substrate and has apertures formed so as to be positioned above respective photoelectric conversion units, and a high refractive index layer formed in the apertures. Here, each aperture has a smaller aperture width than a maximum wavelength in a wavelength of light in a vacuum converted from a wavelength of the light entering the photoelectric conversion unit through the apertures, and the high refractive index is made of a high refractive index material having a refractive index which allows transmission of light having the maximum wavelength through the aperture.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: June 28, 2011
    Assignee: Panasonic Corporation
    Inventors: Takumi Yamaguchi, Takahiko Murata, Shigetaka Kasuga
  • Patent number: 7968456
    Abstract: A semiconductor interconnect structure and method providing an embedded barrier layer to prevent damage to the dielectric material during or after Chemical Mechanical Polishing. The method employs a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to protect the dielectric material from the CMP process as well as subsequent etch, clean and deposition steps of the next interconnect level.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Paul S. McLaughlin, Sujatha Sankaran, Theodorus E. Standaert
  • Patent number: 7964896
    Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Edward W. Kiewra, Steven J. Koester, Devendra K. Sadana, Ghavam Shahidi, Yanning Sun
  • Patent number: 7960199
    Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: June 14, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Young Seok Choi, Byung Yong Ahn, Ki Su Cho, Hong Woo Yu
  • Patent number: 7960789
    Abstract: An integrated field-effect transistor is described in which a substrate region is surrounded by: two terminal regions (a source region and a drain region), two electrically insulating layers, two electrically insulating regions, and an electrically conductive connecting region. The insulating layers are arranged at mutually opposite sides of the substrate region and are adjoined by control regions. The insulating regions are arranged at mutually opposite sides of the substrate region. The electrically conductive connecting region produces an electrically conductive connection between one terminal region and the substrate region. The connecting region includes a metal-semiconductor compound. Part of a covering area of the substrate region is covered by the connecting region, which extends further over a covering area of the source region. The part of the covering area of the substrate region covers the substrate region between the two insulating layers and between the two control regions.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: June 14, 2011
    Assignee: Infineon Technologies AG
    Inventor: Ronald Kakoschke
  • Patent number: 7960740
    Abstract: A structure of a light emitting diode is provided. The light emitting diode comprises a light emitting diode die; two conductive frames electronically and respectively connecting to the cathode and anode of the light emitting diode die, and two substrates. Each conductive frame has a fixing hole and each substrate has a protrusive pillar. The upper opening of the fixing hole is broader than the bottom opening. The protrusive pillar is inserted into the fixing hole and the shape of the protrusive pillar is deformed for fitting and binding with the fixing hole.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: June 14, 2011
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Sheng-Jia Sheu, Chien-Chang Pei
  • Patent number: 7960771
    Abstract: A memory element is formed by providing an organic compound between a pair of upper and lower electrodes. However, when the electrode is formed over a layer containing an organic compound, a temperature is limited because the layer containing the organic compound can be influenced depending on a temperature for forming the electrode. A forming method for the electrode is limited due to this limitation of a temperature. Therefore, there are problems that an expected electrode cannot be formed, and miniaturization of an element is inhibited. A semiconductor device includes a memory element and a switching element which are provided over a substrate having an insulating surface. The memory element includes first and second electrodes, and a layer containing an organic compound, which are provided on the same plane. A current flows from the first electrode to the second electrode. The first electrode is electrically connected to the switching element.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: June 14, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Takehisa Sato
  • Patent number: 7955878
    Abstract: A semiconductor light emitting device can include a casing having a concave-shaped cavity with an opening, a semiconductor light emitting element installed in a bottom portion of the cavity, and a resin layer for filling an interior of the cavity. The resin layer can include a wavelength conversion material, and can be formed in a convex shape in a light radiation direction of the light emitting element. In the resin layer a layer with a high density of the wavelength conversion material can be formed near a surface of the convex shape.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: June 7, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Mitsunori Harada
  • Patent number: 7956453
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor package including one or more semiconductor dies which are electrically connected to an underlying substrate through the use of a conductive pattern which is at least partially embedded in a patterning layer of the package. In a basic embodiment of the present invention, the semiconductor package comprises a substrate having a conductive pattern disposed thereon. Electrically connected to the conductive pattern of the substrate is at least one semiconductor die. The semiconductor die and the substrate are at least partially encapsulated by a patterning layer. Embedded in the patterning layer is a wiring pattern which electrically connects the semiconductor die to the conductive pattern. A portion of the wiring pattern is exposed in the patterning layer.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: June 7, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Do Hyeong Kim, Bong Chan Kim, Yoon Joo Kim, Ji Young Chung
  • Patent number: 7952134
    Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeol Byun, Chan-Kwang Park, Jae-Hwan Moon, Tae-Wan Lim, Seung-Ah Kim
  • Patent number: 7952112
    Abstract: A submount for red, green, and blue LEDs is described where the submount has thermally isolated trenches and/or holes in the submount so that the high heat generated by the green/blue AlInGaN LEDs is not conducted to the red AlInGaP LEDs. The submount contains conductors to interconnect the LEDs in a variety of configurations. In one embodiment, the AlInGaP LEDs are recessed in the submount so all LEDs have the same light exit plane. The submount may be used for LEDs generating other colors, such as yellow, amber, orange, and cyan.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: May 31, 2011
    Assignee: Philips Lumileds Lighting Company LLC
    Inventor: Franklin J. Wall, Jr.
  • Patent number: 7952183
    Abstract: A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: May 31, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Okada, Kiyokazu Okada
  • Patent number: 7952094
    Abstract: An electro-optical device including a substrate, data lines and scanning lines, thin film transistors being disposed below the data lines and above the substrate. Storage capacitors are disposed over the data lines in a region opposite to the channel region of the thin film transistors in plan view. Each storage capacitor has a pixel-potential-side electrode, a dielectric film, and a fixed-potential-side electrode that have been formed sequentially. The pixel electrodes are disposed over the storage capacitors so as to correspond to the data lines and the scanning lines on the substrate in plan view, and the pixel electrodes are electrically connected to the pixel-potential-side electrodes and the thin film transistors. This abstract is intended only to aid those searching patents, and is not intended to be used to interpret or limit the scope or meaning of the claims in any manner.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 31, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Yasuji Yamasaki
  • Patent number: 7948071
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 24, 2011
    Assignee: Qimonda AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Patent number: 7943932
    Abstract: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected with the channel layer; a first stress absorbing layer below the thin film transistor; a first protection layer on the first stress absorbing layer; a second stress absorbing layer on the thin film transistor; a second protection layer on the second stress absorbing layer; and a pixel electrode on the second protection layer, the pixel electrode being connected with the drain electrode.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: May 17, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Yong In Park, Seung Han Paek, Sang Soo Kim
  • Patent number: 7943945
    Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: May 17, 2011
    Assignee: Cree, Inc.
    Inventors: Bruce Baretz, Michael A. Tischler
  • Patent number: 7944064
    Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 17, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
  • Patent number: 7943405
    Abstract: A liquid crystal display panel and a fabricating method thereof comprising an image sensing capability, image scanning, and touch inputting. In the liquid crystal display device, a gate line and a data line are formed to intersect each other on a substrate to define a pixel area in which a pixel electrode is positioned. A first thin film transistor is positioned at an intersection area of the gate line and the data line. A sensor thin film transistor senses light having image information and supplied with a first driving voltage from the data line. A driving voltage supply line is positioned in parallel to the gate line to supply a second driving voltage to the sensor thin film transistor.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 17, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hee Kwang Kang, Kyo Seop Choo
  • Patent number: 7939908
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 10, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
  • Patent number: 7935543
    Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 3, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore S. Moise, IV, Scott R. Summerfelt, Kezhakkedath R. Udayakumar