Patents Examined by Wael M. Fahmy
  • Patent number: 7943945
    Abstract: A light emitting assembly comprising a solid state device coupleable with a power supply constructed and arranged to power the solid state device to emit from the solid state device a first, relatively shorter wavelength radiation, and a down-converting luminophoric medium arranged in receiving relationship to said first, relatively shorter wavelength radiation, and which in exposure to said first, relatively shorter wavelength radiation, is excited to responsively emit second, relatively longer wavelength radiation. In a specific embodiment, monochromatic blue or UV light output from a light-emitting diode is down-converted to white light by packaging the diode with fluorescent organic and/or inorganic fluorescers and phosphors in a polymeric matrix.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: May 17, 2011
    Assignee: Cree, Inc.
    Inventors: Bruce Baretz, Michael A. Tischler
  • Patent number: 7944064
    Abstract: A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: May 17, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Shinji Wakisaka, Tomohiro Ito, Shigeru Yokoyama, Osamu Kuwabara, Norihiko Kaneko, Syouichi Kotani
  • Patent number: 7943405
    Abstract: A liquid crystal display panel and a fabricating method thereof comprising an image sensing capability, image scanning, and touch inputting. In the liquid crystal display device, a gate line and a data line are formed to intersect each other on a substrate to define a pixel area in which a pixel electrode is positioned. A first thin film transistor is positioned at an intersection area of the gate line and the data line. A sensor thin film transistor senses light having image information and supplied with a first driving voltage from the data line. A driving voltage supply line is positioned in parallel to the gate line to supply a second driving voltage to the sensor thin film transistor.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 17, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hee Kwang Kang, Kyo Seop Choo
  • Patent number: 7939908
    Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 10, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
  • Patent number: 7935543
    Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 3, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore S. Moise, IV, Scott R. Summerfelt, Kezhakkedath R. Udayakumar
  • Patent number: 7936055
    Abstract: An integrated circuit package system is provided including forming a first external interconnect and a die paddle having a slot, forming an inner terminal from a peripheral region of the die paddle, connecting an integrated circuit die and the peripheral region for ground connection, and molding through the slot.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: May 3, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Pandi Chelvam Marimuthu
  • Patent number: 7932519
    Abstract: A pixel structure includes a scan line, a data line, a gate electrode, a semiconductor layer, a source electrode, a drain electrode including a comb-shaped part surrounding the source electrode and a connecting part, and a pixel electrode electrically connected to the drain electrode. The scan line and the data line are arranged intersectedly and electrically insulated from each other. At least a portion of the source electrode and the drain electrode are disposed on the semiconductor layer. At least one branch of the comb-shaped part extends outside one side of the gate electrode to form a protrusion part. The connecting part extends from the comb-shaped part beyond the other side of the gate electrode. The protrusion part and the connecting part aligned with the margin of the gate electrode have a first width and a third width respectively, wherein the first width substantially equals to the third width.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 26, 2011
    Assignee: Century Display(ShenZhen)Co.,Ltd.
    Inventor: Chih-Chung Liu
  • Patent number: 7932590
    Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 26, 2011
    Assignee: Atmel Corporation
    Inventor: Ken M. Lam
  • Patent number: 7932598
    Abstract: A semiconductor module has a housing (2) and a metal base plate (3). A reliable yet easily producible force-transmitting connection between a semiconductor module and an external heat sink is provided by a mechanical pressure-proof counterpart (4) which is incorporated into the housing (2) and forms a firm connection (14) with a pressure-proof connecting element (10) on the base plate side. The connection is provided with a passage opening (12) for fastening the semiconductor module to the heat sink.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: April 26, 2011
    Assignee: Infineon Technologies AG
    Inventor: Andreas Lenniger
  • Patent number: 7928473
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 19, 2011
    Assignee: An Elbit Systems-Rafael Partnership
    Inventor: Philip Klipstein
  • Patent number: 7928455
    Abstract: A semiconductor light-emitting device includes a light-impervious substrate, a bonding structure, a semiconductor light-emitting stack, and a fluorescent material structure overlaying the semiconductor light-emitting stack. The semiconductor light-emitting stack is separated from a growth substrate and bonded to the light-impervious substrate via the bonding structure. A method for producing the semiconductor light-emitting device includes separating a semiconductor light-emitting stack from a growth substrate, bonding the semiconductor light-emitting stack to a light-impervious substrate, and forming a fluorescent material structure over the semiconductor light-emitting stack.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 19, 2011
    Assignee: Epistar Corporation
    Inventors: Min-Hsun Hsieh, Chia-Fen Tsai
  • Patent number: 7923824
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7923836
    Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Tien-Jen Cheng, Roger A. Quon
  • Patent number: 7923810
    Abstract: A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element hole on the second exposed portion of the semiconductor region.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Won Ha, Sang-Yoon Kim
  • Patent number: 7919374
    Abstract: A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is a semiconductor device of a super-junction structure, including: a gate electrode filled in a trench formed on a semiconductor substrate; a gate wiring metal forming a surface layer; and a gate electrode plug connecting between the gate electrode and the gate wiring metal. Thus, a polysilicon layer necessary for the conventional typical power MOSFET is unnecessary. That is, column regions of an element active portion and an outer peripheral portion can be formed under the same conditions. As a result, it is possible to improve an element breakdown voltage as compared with the conventional one.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: April 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hitoshi Ninomiya, Yoshinao Miura
  • Patent number: 7919833
    Abstract: There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: April 5, 2011
    Assignee: Nepes Corporation
    Inventor: Yun Mook Park
  • Patent number: 7915085
    Abstract: A method and apparatus for coating a plurality of semiconductor devices that is particularly adapted to coating LEDs with a coating material containing conversion particles. One method according to the invention comprises providing a mold with a formation cavity. A plurality of semiconductor devices are mounted within the mold formation cavity and a curable coating material is injected or otherwise introduced into the mold to fill the mold formation cavity and at least partially cover the semiconductor devices. The coating material is cured so that the semiconductor devices are at least partially embedded in the cured coating material. The cured coating material with the embedded semiconductor devices is removed from the formation cavity. The semiconductor devices are separated so that each is at least partially covered by a layer of the cured coating material.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: March 29, 2011
    Assignee: Cree, Inc.
    Inventors: Michael S. Leung, Eric J. Tarsa, James Ibbetson
  • Patent number: 7915713
    Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Juergen Faul, Juergen Holz
  • Patent number: 7915692
    Abstract: The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the sourcedrain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the sourcedrain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 7910916
    Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: March 22, 2011
    Assignee: Kyocera Corporation
    Inventors: Koichiro Niira, Hirofumi Senta, Hideki Hakuma