Abstract: An AMOLED doubled-sided display includes an OLED array layer that includes a plurality of top-emitting OLED units and a plurality of bottom-emitting OLED units arranged alternate with each other to form an array. Each of the top-emitting OLD units and the bottom-emitting OLED units has different thickness for respective anodes and cathodes, to realize the top-emitting characteristics of the top-emitting OLED units and the bottom-emitting characteristics of the bottom-emitting OLED units. As such, by designing an algorithm for a single IC to control image displaying, only a display panel and a control IC are sufficient to achieve double-sided displaying, and ensure an observer standing in front of the display panel will not see mirrored image or directional distorted image, as well as achieve low-cost and quality display result.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: In a semiconductor device using, as a FWD, a diode formed in a silicon carbide (SiC) substrate, while preventing gate oscillation, an increase of switching loss is suppressed at the time of a temperature increase also. A semiconductor device includes: a transistor element; a diode element formed in a SiC substrate; and a resistive element that is electrically connected to a gate of the transistor element, and has a resistor temperature coefficient which is within the range of ±150×10?6/K. The resistive element has a resistor formed of a ceramic-containing material.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: The present disclosure discloses an OLED encapsulation structure, a display device and a method for manufacturing an OLED encapsulation structure. The OLED encapsulation structure includes an OLED device and a plurality of film layers covering the OLED device. The plurality of film layers includes an inorganic layer and an organic layer stacked alternately, and contacting surfaces of any two film layers in contact with each other among the plurality of film layers include complementary topographies such that the any two film layers in contact with each other are stuck with each other.

Abstract: A method of producing a semiconductor component includes applying an auxiliary carrier at a first side of a semiconductor body, the auxiliary carrier having a first lateral coefficient of thermal expansion, and applying a connection carrier at a second side of the semiconductor body facing away from the auxiliary carrier, the connection carrier having a second lateral coefficient of thermal expansion, wherein the semiconductor body is grown on a growth substrate different from the auxiliary carrier, the first and the second lateral coefficient of thermal expansion differ by at most 50%, and the growth substrate is removed prior to application of the auxiliary carrier.

Abstract: A method of forming a conductive area at a top surface of a light-emitting diode includes: preparing a substrate having a top surface with a conductive pad thereon; bonding a light-emitting diode having first and second type semiconductor layers and an active layer to the conductive pad; forming a polymer layer on the substrate such that a difference between a distance from a first surface of the polymer layer to the top surface of the substrate and a distance from a second surface of the polymer layer to a top surface of the light-emitting diode is greater than a distance from an interface between a second type semiconductor layer and an active layer to the top surface of the substrate; and etching the polymer layer till the second type semiconductor layer to expose the top surface of the light-emitting diode from the polymer layer.

Abstract: A thin film transistor is provided and includes an active layer, a source electrode, a drain electrode, a gate electrode and a gate electrode insulating layer, the active layer includes a source electrode region, a drain electrode region and a channel region, the source electrode region and the drain electrode region include a first metal material, and the channel region includes a semiconductor material made from oxidation of the first metal material.

Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.

Abstract: A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.

Abstract: Methods for depositing a doped metal carbide film on a substrate are disclosed. The methods may include: depositing a doped metal carbide film on a substrate utilizing at least one deposition cycle of a cyclical deposition process; and contacting the doped metal carbide film with a plasma generated from a hydrogen-containing gas. Semiconductor device structures including a doped metal carbide film formed by the methods of the disclosure are also disclosed.

Abstract: A display apparatus and a method of manufacturing the same are disclosed. The display apparatus includes at least one light emitting diode chip, a conductive portion disposed under the light emitting diode chip and coupled to the light emitting diode chip, and an insulating material surrounding the conductive portion. The conductive portion includes a first conductive portion and a second conductive portion, and the insulating material is formed to expose at least a portion of the upper surfaces of the first conductive portion and the second conductive portion.

Abstract: Methods for depositing an amorphous carbon layer on a substrate are described. A substrate is exposed to a carbon precursor having a structure of Formula (I). Also described are methods of etching a substrate, including forming an amorphous carbon hard mask on a substrate by exposing the substrate to a carbon precursor having the structure of Formula (I).

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Protruding tip portions are formed on each of the sacrificial material layers around the memory openings. A plurality of insulating spacers is formed within each memory opening between each vertically neighboring pair of tip portions of the sacrificial material layers. A phase change memory material and a vertical bit line are formed within each of the memory openings. The phase change memory material can be formed as a vertical stack of discrete annular phase change memory material portions, or can be formed as a continuous phase change memory material layer. Each of the sacrificial material layer can be replaced by an electrically conductive layer.

Abstract: A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

Abstract: One embodiment of the present disclosure provides an organic light-emitting element corresponding to each pixel region. The organic light-emitting element includes a hole transport layer, a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, a fourth light-emitting layer, and an electron transport layer. The first light-emitting layer includes a first dopant corresponding to a first color and a first host. The second light-emitting layer includes a second dopant corresponding to a second color different from the first color and a second host different from the first host. The third light-emitting layer includes the first dopant and the second host, and the fourth light-emitting layer includes the second dopant and the second host.

Abstract: Semiconductor device, static random access memory (SRAM), and their fabrication methods are provided. The semiconductor device includes a base substrate with first fins formed in adjacent device regions. An isolation structure is formed on the base substrate having a top lower than the first fins. The isolation structure includes a first region and a second region, on opposite sidewalls of a corresponding first fin. The first region is between the adjacent first fins. The isolation structure has a top in the first region higher than that in the second region. A first doped layer is formed in the first fin having a portion in the second region. A dielectric layer is formed over the base substrate and a first contact hole is formed in the dielectric layer to expose a top of the first doped layer and a sidewall surface of the first doped layer, in the second region.

Abstract: A light emitting device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a cathode, a layer comprising a material capable of transporting and injection electrons comprising an inorganic material, an emissive layer comprising quantum dots, a layer comprising a material capable of transporting holes, a layer comprising a hole injection material, and an anode. In certain embodiments, the hole injection material can be a p-type doped hole transport material. In certain preferred embodiments, quantum dots comprise semiconductor nanocrystals. In another aspect of the invention, there is provided a light emitting device wherein the device has an initial turn-on voltage that is not greater than 1240/?, wherein ? represents the wavelength (nm) of light emitted by the emissive layer. Other light emitting devices and a method are disclosed.

Abstract: A display apparatus includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixels connected to the gate lines and the data lines. Each of the pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed in an i-th row and a fourth sub-pixel disposed in an (i+1)-th row. The first, second, and third sub-pixels and the fourth sub-pixel are disposed with the i-th gate line between the fourth sub-pixel and the first, second, and third sub-pixels and connected to the i-th gate line, and the first, second, third, and fourth sub-pixels are connected to different data lines from each other.