Abstract: A method for producing optoelectronic semiconductor devices and an optoelectronic semiconductor device are disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips for producing electromagnetic radiation, arranging the plurality of semiconductor chips in a plane, forming a housing body composite, at least some regions of which are arranged between the semiconductor chips, forming a plurality of conversion elements, wherein each conversion element comprises a wavelength-converting conversion material and is arranged on one of the semiconductor chips, encapsulating the plurality of conversion elements at least on their lateral edges by an encapsulation material, and separating the housing body composite into a plurality of optoelectronic semiconductor components.

Abstract: To improve the particle size regulation produced by a coffee grinder (64) associated with an espresso coffee dispensing machine (10), a method is described comprising the steps of acquiring, via a sensor (42), a data or an electrical signal indicative of the shape of the thread of liquid coffee (C) while it percolates from the outlet (14) of the machine, driving an operator of the grinder to regulate the particle size thereof as a function of the detected signal or data.

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Abstract: A semiconductor structure includes a first substrate, a second substrate disposed over the first substrate, and including a first surface, a second surface opposite to the first surface, a via portion extending between the first surface and the second surface, a first through hole and a second through hole, and a device disposed over the second surface, and including a dielectric layer, a backplate at least partially exposed from the dielectric layer and a membrane at least partially exposed from the dielectric layer and disposed between the backplate and the first substrate, wherein the via portion is disposed within the second through hole, and the dielectric layer is bonded with the second substrate, and the device is electrically connected to the first substrate through the via portion.

Abstract: A method for controlling at least one device in at least one building includes: selectively transferring, by a control system comprising a server and a number of gateways, at least one application from the server to a particular gateway or from a particular gateway to the server based on at least one transfer rule; and controlling, by the control system, the at least one device via the at least one application.

Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

Abstract: A memory structure includes a substrate, a plurality of stacks, a plurality of memory layers, a plurality of channel layers and a plurality of pad layers. The stacks are disposed on the substrate. The stacks are separated from each other by a plurality of first trenches. The stacks include alternately arranged first stacks and second stacks. Each of the stacks includes alternately stacked conductive strips and insulating strips. The memory layers are partially disposed in the first trenches. The memory layers extend onto the stacks in a conformal manner. The channel layers are disposed on the memory layers in a conformal manner. The pad layers are at least disposed on the channel layers at positions substantially above the first stacks.

Abstract: A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Abstract: A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball.

Abstract: A method according to embodiments of the invention includes growing on a first surface of a sapphire substrate a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure is formed into a plurality of LEDs. Cracks are formed in the sapphire substrate. The cracks extend from the first surface of the sapphire substrate and do not penetrate an entire thickness of the sapphire substrate. After forming cracks in the sapphire substrate, the sapphire substrate is thinned from a second surface of the sapphire substrate. The second surface is opposite the first surface.

Abstract: A package for mounting a light emitting element includes a pair of lead electrodes and a resin molded body. The pair of lead electrodes are made of metal plates. The package has a recess portion in which a light emitting element is mounted. The recess portion is formed of the pair of lead electrodes and the resin molded body. The pair of lead electrodes are exposed on a bottom surface of the recess portion. At least one of the pair of lead electrodes has a groove portion that is formed along a periphery of the metal plate exposed on the bottom surface of the recess portion. The periphery of the at least one of the pair of lead electrodes on the bottom surface of the recess portion constitutes a boundary between the bottom surface of the recess portion and a side surface portion of the recess portion.

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

Abstract: A flexible link system and approach for dynamically switching among wall modules of various types without re-engineering an associated controller application. Some of the types of wall modules may incorporate those of Sylk, BACnet and conventional types. A wall module type switching mechanism may incorporate a controller incorporating an application having a flexible link for the connection of wall modules of various types. The flexible link may enable a number of data points of the application to be applicable to various types of wall modules in that switching from a wall module of one type to a wall module of another type does not necessarily require another set of data points in the application.

Abstract: The present disclosure provides an OLED display panel, an electronic device, and a manufacturing method. The OLED display panel comprises a substrate, a first electrode, a light-emitting function layer, and a second electrode including Ag or a metal alloy containing Ag. When the second electrode is made of the metal alloy containing Ag, a content of Ag in the second electrode is more than a sum of contents of all other elements in the second electrode.

Abstract: A micro gas chromatograph includes one or more separator columns formed within a device layer. The separator columns have small channel cross sections and long channel lengths with atomic-smooth channel sidewalls enabling a high channel packaging density, multiple channels positioned on top of each other, and channel segments that are thermally decoupled from the substrates. The micro gas-chromatograph also enables electrostatic and thermal actuators to be positioned in close proximity to the separator columns such that the material passing through the columns is one or more of locally heated, locally cooled, and electrically biased.

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: The invention relates to a method for generating a digital model (6) of a dental replacement part, formed by a dental prosthesis and a prosthesis base having a rear protection plate, and for producing a dental replacement part of this type, wherein, in a digital model (1) of a jawbone to be provided and a digital dental prosthesis model (2) positioned therein, an interface (3) is automatically and/or manually marked in the region of the dental prosthesis model (2), a rear protection plate model (4) is formed by the interface (3), an abutting surface (1?) of the digital jawbone model (1) and a region of a surface (2?) of the dental prosthesis model (2) joining the surface (1?) and the interface (3), a revised dental prosthesis model (5) is formed from the digital dental prosthesis model (2) by adopting the interface (3) as a surface, and the digital model (6) of the dental replacement part is created from the rear protection plate model (4) and the revised dental prosthesis model (5).

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.