Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.

Abstract: A display device includes: a base layer; pixel electrodes laminated on the base layer; a light emitting element layer laminated on the pixel electrodes; and a common electrode laminated on the light emitting element layer. Each of the pixel electrodes includes a first oxide conductive layer that is in direct contact with the base layer, a metal conductive layer that is in direct contact with the first oxide conductive layer, and a second oxide conductive layer that is in direct contact with the metal conductive layer. The base layer has an adhesion to the first oxide conductive layer that is higher than that of the metal conductive layer. The first oxide conductive layer includes a protrusion part that is extended farther than the metal conductive layer and the second oxide conductive layer in a direction, adjacent two of the pixel electrodes facing each other in the direction.

Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Abstract: A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.

Abstract: A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: The present disclosure relates to optical receiver systems. An example optical receiver system includes a first substrate with a plurality of photodetectors and a bias circuit. The bias circuit is electrically coupled to each photodetector of the plurality of photodetectors. The bias circuit is configured to provide a bias voltage to each photodetector. The optical receiver system also includes a plurality of capacitors. Each capacitor of the plurality of capacitors is electrically-coupled to a respective photodetector of the plurality of photodetectors. The optical receiver system also includes a second substrate with a read-out circuit having a plurality of channels. Each channel of the plurality of channels is capacitively-coupled to a respective photodetector via the respective capacitor.

Abstract: A compound semiconductor device includes: a semiconductor substrate; a channel layer over the semiconductor substrate; a carrier supply layer over the channel layer; and a gate electrode, a source electrode and a drain electrode above the carrier supply layer. The semiconductor substrate includes an impurity-containing region containing an impurity, the impurity forms a level lower than a lower edge of a conduction band of silicon by 0.25 eV or more, the impurity forms the level higher than an upper edge of a valence band of silicon.

Abstract: A semiconductor light emitting device package includes a light emitting structure having a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first surface, and a second surface, a first electrode and a second electrode disposed on the second surface of the light emitting structure; an insulating layer, a first metal pad and a second metal pad disposed on the insulating layer, and each having a surface with a first fine uneven pattern so as to have a first surface roughness, a first bonding pad and a second bonding pad disposed on the first metal pad and the second metal pad, respectively, and each having a surface with a second fine uneven pattern so as to have a second surface roughness, and an encapsulant encapsulating the first bonding pad, the second bonding pad, the first metal pad, and the second metal pad.

Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

Abstract: A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric structure is disposed over the substrate. The dielectric structure has a through via hole passing through the dielectric structure, and a sidewall of the through via hole includes at least one indentation. The barrier layer conformally covers the sidewall and a bottom of the through via hole. The glue layer conformally covers the barrier layer. The copper seed layer conformally covers the glue layer. The copper layer covers the copper seed layer and fills the through via hole.

Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.

Abstract: The present disclosure relates to a method for the application of an antiwetting coating on at least one surface of a substrate of semiconductor material comprising the steps of: a) applying on said at least one surface a metal layer of a material chosen in the group constituted by noble metals, coining metals, their oxides and their alloys; and b) applying on said metal layer a layer of a thiol of formula R—SH, where R is a linear alkyl chain having from 3 to 20 carbon atoms and, optionally, at least one hetero-atom, for obtaining an antiwetting coating. The disclosure further regards a method for the production of a nozzle plate for ink-jet printing and to an integrated ink-jet printhead provided with a nozzle plate obtained according to the method of the disclosure.

Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to diodes offering orientation control properties in a fluidic assembly system.

Abstract: An insulated gate bipolar transistor device includes a semiconductor substrate having a drift region of an insulated gate bipolar transistor structure, a first fin structure starting from the drift region of the semiconductor substrate and extending orthogonal to a main surface of the semiconductor substrate, and a first gate structure of the insulated gate bipolar transistor structure extending alma at least a part of the first fin structure.

Abstract: An event location analysis system includes a first wireless terminal device. The first wireless terminal device includes a first measurement unit, a second measurement unit, and a first processor. The second measurement unit consumes larger amounts of power than the first measurement unit consumes. The first processor is configured to transmit a first notification signal upon detecting a first event on basis of a measurement value of the first measurement unit. The first processor is configured to start the second measurement unit upon receiving a second notification signal. The first processor is configured to activate a measurement operation of the first measurement unit and a measurement operation of the second measurement unit after the second measurement unit is started. The first processor is configured to stop the measurement operation of the second measurement unit after a predetermined time has elapsed since the start of the second measurement unit.

Abstract: An image sensor including a color splitter and a method of manufacturing the image sensor is provided. The image sensor includes a photoelectric conversion layer; a plurality of color filters disposed on the photoelectric conversion layer; a light transmission layer disposed on the photoelectric conversion layer and the plurality of color filters; and a color splitter that is disposed on the light transmission layer, comprises a top surface and a side surface exposed to ambient air, and is configured to transmit a portion of light incident on the color splitter toward a first pixel region and refract a remaining portion of the incident light toward second pixel regions adjacent to the first pixel region, according to a difference between a refractive index of the color splitter and a refractive index of the ambient air.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.