Abstract: A light-emissive polymer device comprising: an anode; a cathode; a conjugated light-emissive polymer layer located between the anode and the cathode; and a driver for applying a voltage drive scheme between the anode and the cathode of a pattern having a relatively high voltage portion which causes the polymer layer to emit light and a relatively low voltage portion during which substantially no light is emitted by the polymer layer.

Abstract: A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants.

Abstract: A magnetoresistive element comprises an n-type emitter layer, a p-type base layer, and an n-type collector layer, the three layers being so arranged as to form a pn-junction with each other, an emitter ferromagnetic layer formed in contact with the n-type emitter layer, a base ferromagnetic layer formed in contact with the p-type base layer, a power source for applying, by way of the emitter ferromagnetic layer, a forward bias voltage between the n-type emitter layer and the p-type base layer, a power source for applying a backward bias voltage to the n-type collector layer and the p-type base layer and a power source for applying, by way of the base ferromagnetic layer, a bias voltage so as to inject minority carriers into the p-type base layer.

Abstract: A charge coupled device includes a substrate, a photoelectric conversion region, a hole accumulation region, a vertical charge coupled region, and a buried transmission gate region. The substrate includes a surface with a light receiving region and a charge transmission region. The photoelectric conversion region is provided in a substrate beneath the light receiving and charge transmission regions, and the photoelectric conversion region generates a photoelectric signal responsive to light received at the light receiving region of the substrate surface. The hole accumulation region is provided in the substrate between the photoelectric conversion region and the light receiving region of the substrate surface. The vertical charge coupled region is provided in the substrate between the photoelectric conversion region and the charge transmission region of the substrate surface. The buried transmission gate region is provided between the vertical charge coupled region and the photoelectric conversion region.

Abstract: A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulating layer in the memory division. The insulating layer separates the memory cells from the underlying substrate such that the leakage current that can otherwise occur therebetween can be prevented. Moreover, the coding process is performing by forming contact windows at selected locations rather than by performing ion-implantation as in conventional methods. The fabrication process is thus easy to perform. Since the memory cells are diode-based rather than MOSFET-based, the punch-through effect that usually occurs in MOSFET-based memory cells can be prevented. The diode-based structure also allows the packing density of the memory cells on the ROM device to be dependent on the line width of the polysilicon layers in the ROM device.

Abstract: Disclosed are articles that comprise an oxide layer on a GaAs-based semiconductor body, with metal layers on the oxide and the body facilitating application of an electric field across the oxide layer. The interface between the oxide and the semiconductor body is of device quality. Contrary to teachings of the prior art, the oxide is not essentially pure Ga.sub.2 O.sub.3, but instead has composition Ga.sub.x A.sub.y O.sub.z, where A is an electropositive stabilizer element adapted for stabilizing Ga in the 3+ oxidation state. Furthermore, x.gtoreq.0, z is selected to satisfy the requirement that both Ga and A is substantially fully oxidized and y/(x+y) is greater than 0.1. Stabilizer element A typically is selected from Sc, Y, the rare earth elements and the alkaline earth elements. Articles according to the invention exemplarily comprise a planar enchancement mode MOS-FET with inversion channel. A method of making articles as described above is also disclosed.

Abstract: A semiconductor device has a light-emitting diode covered by a transparent spacer which separates the LED from a uniformly thick fluorescent material containing layer such that there is a more uniform lighting of the fluorescent material containing layer to provide a uniform white light.

Abstract: A solid state image pickup device includes a semiconductor substrate, a CCD channel region in the semiconductor substrate, a plurality of polygates over the CCD channel regions, and a photoelectric conversion region having a portion above an uppermost surface of the semiconductor substrate.

Abstract: A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.

Abstract: A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.

Abstract: An organic light emitting diode having a lower electrode formed on a glass substrate, and an emissive layer and an upper electrode formed atop each other on the lower electrode. A thin insulating layer is disposed between the emissive layer and the lower or upper electrode. The thin insulating layer has a thickness within a range where tunneling occurs. The thin insulating layer is inserted between the emissive layer and electrode, so as to balance the injection of electrons a holes into the emissive layer.

Abstract: A semiconductor light emitting device comprises: a plurality of II-VI compound semiconductor layers stacked on a semiconductor substrate; a contact layer formed on the II-VI compound semiconductor layers; a first first-conduction-type-side electrode and a second first-conduction-type-side electrode formed on the contact layer; and a second-conduction-type-side electrode formed on a bottom surface of the semiconductor substrate, at least a portion of the contact layer underlying the second first-conduction-type-side electrode being changed to a high-resistance region by application of an electric field between the second first-conduction-type-side electrode and the second-conduction-type-side electrode, and the high-resistance region behaving as a current blocking region.

Abstract: A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Abstract: The present invention includes a process of growing a compound semiconductor layer locally, after applying radical particles that do not become an etchant of a compound semiconductor layer to an insulating mask so as to terminate the surface of the insulating mask in a state that the compound semiconductor layer is covered with the insulating mask, on the surface of the compound semiconductor layer exposed from the insulating mask.

Abstract: A semiconductor device comprises a GaAs substrate 10; a buffer layer 12 formed on the GaAs substrate 10 and having a wider band gap than that of InGaP; a channel layer 14 formed on the buffer layer 12 and formed of an InGaP; a gate electrode 34 for controlling current of the channel layer 14. InGaP has a high carrier mobility and large .GAMMA.-L energy difference. Accordingly, the channel layer is formed of InGaP, whereby the semiconductor device which is operable at high speed and high voltage can be obtained.

Abstract: A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed of semi-insulating GaAs. A gate electrode is formed on a specified region of the top surface of the heterojunction epitaxial layer. The source/drain formation regions of the heterojunction epitaxial layer are provided with respective high-concentration N-type impurity diffusion regions, on which respective ohmic electrodes are formed.

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region, a base region overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region a surface region, and a first vertical diffusion region connecting the buried layer to the surface region. A second vertical diffusion region connects the buried emitter layer periphery to a first surface contact, while the surface emitter region is contacted, along three peripheral sides thereof, by a second surface contact. The transistor current flows from the substrate, through the base to the buried emitter region. It is then conveyed into the vertical region, which represents a resistive path, and on reaching the surface region splits between two resistive paths included between the vertical region and the surface contacts.

Abstract: A compound semiconductor device includes a substrate and a group III-V compound semiconductor layer provided on the substrate, wherein the group III-V compound semiconductor layer contains As as a group V element and Tl as a group III element.

Abstract: A method for fabricating a bipolar transistor comprising the steps of: implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the further step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material.

Abstract: In a thin film capacitor of a random access memory including a lower electrode, a dielectric film and an upper electrode, generation of defects in the dielectric film is suppressed. In another way, impurity diffusion into the dielectric film is prevented. In still another way, lattice matching of the dielectric film and the electrodes is realized. Thus, a reduced dielectric constant of the capacitor is prevented, and a quality of the semiconductor device is increased.