Abstract: A method of fabricating a semiconductor light emitting device includes fabricating, semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.

Abstract: First and second gate electrodes are formed spaced from each other on a semiconductor substrate. A pair of impurity diffusion layers are provided on both sides of the first gate electrode at the surface of the semiconductor substrate. The first gate electrode includes a first lower conductive film, a first protective conductive film provided on the first lower conductive film, and a first upper conductive film provided on the first protective conductive film. The second gate electrode includes a second lower conductive film, a second protective conductive film provided on the second lower conductive film, and a second upper conductive film provided on the second protective conductive film. The second upper conductive film extends to be in contact with one of the pair of impurity diffusion layers.

Abstract: A MOS transistor includes a semiconductor substrate of a first conductivity type having a major surface, a source and drain of a second conductivity type formed on the major surface to define a channel region therebetween, and a gate arranged in the channel region via an insulating film. The MOS transistor includes an impurity-implanted region of the first conductivity type located at a substrate portion which is deeper than the channel region and is shifted to a source side from a region corresponding to the channel region.

Abstract: A pair of source/drain regions are formed on a semiconductor substrate at a predetermined interval. A gate insulator film is formed on the semiconductor substrate between the source/drain regions of the pair. A gate electrode is formed on the gate insulator film. A film for covering the gate electrode and the source/drain regions has a low permeability against water and a hydroxide group, and has a thickness greater than 3 nm and less than 5 nm.

Abstract: A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.

Abstract: The present invention provides a nitride system semiconductor device which decreases cost and improves productivity without heat treatment after the growth and which increases in lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, a p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n layer is 5.times.10.sup.18 cm.sup.-3 or lower.

Abstract: A semiconductor device of planar structure, comprises a pn junction, formed of a first type conducting layer and on top thereof a second type conducting layer, both layers of doped silicon carbide, the edge of the second of the layers being provided with an edge termination (JTE), enclosing stepwise or continuously decreasing effective sheet charge density towards the outer border of the termination, wherein the pn junction and its JTE are covered by a doped or undoped SiC third layer.

Abstract: A solid-state imaging device has a plurality of photodetector elements arranged on a substrate for photoelectrically converting incident light into signal charges, storing the signal charges, and producing an output signal voltage depending on the amount of the stored signal charges. Element-separating electrodes electrically separate adjacent ones of the photodetector elements from each other. Each of the photodetector elements has a control electrode and a gate insulating film below the control electrode. The gate insulating film has a film thickness varying in the width direction of a channel of the gate insulating film.

Abstract: An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device.

Abstract: A first electrode layer is formed on a semiconductor substrate, and surfaces other than a top surface thereof are buried in an insulation film, and the top surface makes the same surface as that of the insulation film. An antifuse insulation film is formed on a flat surface including the top surface of the first electrode layer. A second electrode layer is formed on the antifuse insulation film. An antifuse portion is formed by self-alignment at a cross point between the first and second electrode layers.

Abstract: A semiconductor device having a double spacer and a method of manufacturing the device are provided. The semiconductor device includes a first spacer formed on the sidewall of a gate electrode and a second spacer formed on the slanted sidewall of the first spacer. A first impurity region is formed doped with a first conductivity type impurity at a first concentration and formed at a small junction depth in the substrate to self-align at the edge of the gate electrode. A second impurity region doped with a second conductivity type impurity at a second concentration is formed at a large junction depth in the substrate to self-align at the edge of the first spacer. A third impurity region doped with the first conductivity type impurity at a third concentration is formed at a medium junction depth in the second impurity region to self-align at the edge of the second spacer.

Abstract: A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type GaN. The gate insulating film is made from AlN, which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving a large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a Si-MOS-type FET, resulting in the formation of an inversion layer.

Abstract: A non-volatile two terminal programmable logic element and associated methods for charging and discharging are disclosed. The logic element includes one input and one output terminal, a first capacitor region, a second capacitor region, and a floating gate (transistor-type) structure. The first capacitor region does not permit tunneling. The second capacitor region permits tunneling between its respective electrodes when a predetermined voltage, substantially higher than the normal operating voltage is applied. The source is connected to the input terminal and one electrode of the first capacitor region. The drain is connected to the output terminal and one electrode of the second capacitor region. The floating gate is connected to the other electrodes of the first and second capacitor regions. A programmable logic device constructed from these elements and associated methods of programming and erasing such a device are also shown.

Abstract: Three-dimensional ESD structures are constructed in SOI technology that utilize both bulk devices and thin film SOI devices.

Abstract: A semiconductor integrated circuit device is provided, which is capable of further reduction in chip size without raising any bad effect to the function of the device, and deletion of the TEG region. A test element is formed on a semiconductor substrate. An insulating layer is formed on or over the substrate to cover the test element. An internal circuitry is formed on the substrate. A bonding pad is formed on the insulating layer. The test element is entirely or partially overlapped with the overlying bonding pad. The bonding pad includes a first part and a second part electrically insulated from each other. The first part of the bonding pad is electrically connected to the internal circuitry. The second part of the bonding pad is electrically connected to a terminal of the test element. On a verification test, one of the probes of a tester is contacted with the second part of the bonding pad, and another one thereof is contacted with the first part or an additional part thereof.

Abstract: A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.

Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

Abstract: Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.

Abstract: The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.

Abstract: A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a .?.plat.!. .Iadd.plate .Iaddend.poly material is coated and wrapped.