Abstract: Hot-electron injection driven by a hole impact ionization mechanism at the channel-drain junction provides a new method of hot electron injection. Using this mechanism, a four-terminal pFET floating-gate silicon MOS transistor for analog learning applications provides nonvolatile memory storage. Electron tunneling permits bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. The synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. Synaptic arrays employing these devices enjoy write and erase isolation between array synapses is better than 0.01% because the tunneling and injection processes are exponential in the transistor terminal voltages.

Abstract: A semiconductor light emitting element exhibiting a characteristic of deflected luminous intensity distribution, a semiconductor light emitting device capable of making, even when the element is off the center, a luminous center close to the center, and an element scribing method having a high element separation rate without causing a crack and chipping of pellet edges. The semiconductor light emitting element involves the use of a scribed pellet 10 into which a wafer including a semiconductor layer such as a luminous layer that is stacked on a compound semiconductor substrate inclined at 5.degree. through 20.degree. to a surface (100) in a orientation [011], is subjected to an element separation process by a scribing method.

Abstract: A light emitting device includes a cladding layer composed of a III-V group nitride system semiconductor of a first conductivity type, an active layer formed on the cladding layer of the first conductivity type and composed of a III-V group nitride system semiconductor containing In, an undoped cap layer formed on the active layer and composed of a III-V group nitride system semiconductor, and a cladding layer formed on the cap layer and composed of a III-V group nitride system semiconductor of a second conductivity type.

Abstract: A highly reliable solid-state image pickup device with one- or two-dimensionally arranged connecting portions, capable of avoiding corrosion of wirings resulting from chipping of the substrates and eliminating image defect, is achieved by arranging plural substrates, each bearing a plurality of image taking elements, in a planar manner on a supporting substrate and filling the connecting portions of thus arranged substrates with an organic or inorganic material, of which content in chlorine or in each of sodium and potassium does not exceed 200 ppm.

Abstract: An optical-electronic integrated circuit combining photo detection with an integrated circuit is provided where a light signal input thereto can be directly translated into an electronic signal. The electronic signal can be received and processed by the same integrated circuit. For this optical-electronic integrated circuit, the photo detection circuit is made by a metal-semiconductor-metal process. A current is generated when the photo detection circuit is impinged by photons.

Abstract: An inverter-type basic cell, with a hexagonal contour, comprises one CMOS device pair arrangement including an n-channel transistor and a p-channel transistor. The inverter-type basic cell has a gate region annularly formed and connected in parallel with the n-channel and p-channel transistors, a sectoral drain diffusion region having a vertex at the center of the annularly-formed gate region, and a source diffusion region that is formed outside of the gate region in such a way as to define a shape having two opposing sides that lie on the prolongation of the two radii of the sectoral drain diffusion region.

Abstract: A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.

Abstract: An optoelectronic apparatus has, a die having a mesa (103) with a surface emitting optical device and a metallized p-type contact (209), a planar pad (201) adjacent the mesa for Z-height registration with an optical bench, a first notch (206) having been provided by a first etch and having thereon a metallized n-type contact (208) that is coplanar with the p-type contact (209), a second notch having a side surface (204) having been provided by a second etch, the second notch to abut the optical bench along an x-axis, the first notch (206) extending to the second notch, and the die having side surfaces (207) to abut the optical bench along a y-axis, and the second notch extending to the side surfaces (207).

Abstract: An ohmic electrode for III-V compound semiconductors such as GaAs semiconductors which has practically satisfactory characteristics is disclosed. A non-single crystal InAs layer, Ni film, WSi film and W film are sequentially deposited on an n.sup.+ -type GaAs substrate by sputtering, etc. and subsequently patterned by lift-off, etc. to make a multi-layered structure for fabricating ohmic electrodes. The structure is then annealed first at, e.g. 300.degree. C. for 30 minutes and next at, e.g. 650.degree. C. for one second to fabricate an ohmic electrode.

Abstract: A nitride compound semiconductor light emitting element comprises a substrate, a nitride compound semiconductor n-type layer, a mask layer having a predetermined opening, a nitride compound semiconductor buffer layer epitaxially grown on said n-type layer exclusively at said opening. The buffer layer has a recess on its top face so that a thickness of said buffer layer is thinner above a central portion of the opening and thicker above edge portions of the opening. A nitride compound semiconductor active layer is selectively formed on the recess of the buffer layer to be thicker at the central portion of the recess and thinner at the edges of the recess. A nitride compound semiconductor burying layer overlays the mask layer and the active layer to cover the active layer.

Abstract: An n.sup.- well region is formed at a surface of a semiconductor substrate. A MOS transistor of high breakdown voltage having a drain region and a source region is formed at the surface of the n.sup.- well region. The n.sup.- well region has an impurity concentration peak right below the drain region. Accordingly, a semiconductor device having a high breakdown voltage insulation gate type field effect transistor that can suppress increase of a depletion layer when high voltage is applied across the drain, that can reduce the electric field intensity across the drain, and that has superior breakdown voltage, and a fabrication method thereof, are obtained.

Abstract: Integrated circuit chips having large regions of different device density and topography are susceptible to local processing variations which give rise to systematic failures affecting some circuit regions and not others. Over-simplified test structures cannot signal these failures during processing. Memory chips have large regions of storage cell arrays serviced by sizeable peripheral regions consisting of logic circuits. The device density and configuration in each of these regions on the chip are quite different. During processing steps these regions present differently to the process agents such as chemical etchants and plasmas producing in local variations of processing rates occur which result in systematic under processing in one region or over processing in another. Memory chips are particularly prone to such variations and also lend themselves well to the design of product specific test structures for flagging these aberrations.

Abstract: Each of a plurality of photodiodes forming a photodetector is mounted on a respective metal pad on the surface of a semiconductor integrated circuit chip including a corresponding number of amplifier circuits for detecting the photocurrent from respective photodiodes. Each circuit comprises a high gain, high input impedance amplifier and a feedback element, typically a resistor of high value, connected across the amplifier between input and output nodes thereof. Each photodiode mounting metal pad and each feedback resistor is connected to a common input node of a respective amplifier by metal paths within a connecting structure forming part of the integrated circuit. Adverse effects on the output current from the photodiodes are reduced by forming a junction of the path from each feedback resistor with the path from the corresponding photodiode at the metal pad on which the photodiode is mounted, and interconnecting such junction along a common path to the corresponding amplifier input node.

Abstract: A Read diode includes an inner zone, a cathode zone, an anode zone and a first coupling zone disposed between the inner zone and the anode zone. A second coupling zone is disposed between the first coupling zone and the inner zone. Both coupling zones are used in the reverse mode for dividing an electric field into a high-field zone and a low-field zone and, consequently, permit greatly localized charge carrier generation by impact ionization in the voltage breakdown. The use of the two coupling zones ensures "punch-through" coupling between the high-field and low-field zones which, in contrast to the space charge coupling of Read diodes, permits a largely temperature-independent "soft-recovery" behavior. Hybrid diodes having optimized forward and commutation behaviors can be produced from the FCI-PT diodes. FCI-PT diodes are preferably employed in conjunction with switching power semiconductor components as voltage limiters or freewheeling diodes.

Abstract: A semiconductor memory device includes first and second conductive contact layers (12, 15) and an hydrogenated, silicon-rich, amorphous silicon alloy layer (14), particularly an amorphous silicon nitride or amorphous silicon carbide alloy, extending between the contact layers. A defect band is induced in the amorphous silicon layer which lowers the activation energy level for the transport of carriers through the structure by an amount that is selectable and determined by the defect band. The defect band is created by a programming process, for example, using current stressing or particle bombardment. A memory matrix array device is provided by forming a row and column array of such memory devices from common deposited layers on a common substrate with crossing sets of row and column conductors separated by a layer of the alloy material defining a memory device at each of their cross-over regions.

Abstract: An LED having improved light emission characteristics by allowing radiation generated to be guided towards the side faces of the LED by means of a relatively thick waveguide comprised of a transmissive material, specifically in such a way that as many modes as possible can propagate.

Abstract: A high gain photodetector requiring a substantially silicon area than prior art photodetectors having the same gain. The photodetector includes a light converter for converting a light signal to a current; and a first vertical transistor. The first vertical transistor includes a first well in a semiconductor substrate, the first well including a diffusion region, the semiconductor substrate and the diffusion having a first type of doping and the first well having a second type of doping. The first type of doping is either P-type or N-type, and the second type of doping is the other of the P-type or N-type doping. The light converter is connected to the first well so as to forward bias the vertical transistor thereby causing a current to flow between the diffusion region in the first well and the substrate. Additional amplification of the photocurrent from the light converter can be provided by including a second vertical transistor.

Abstract: A bipolar silicon transistor includes at least one emitter zone with n.sup.+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least one emitter zone. The at least one emitter zone may also have a penetration depth of less than 0.5 .mu.m. A method for producing a bipolar silicon transistor includes implanting a n.sup.+ -doped emitter zone with arsenic, implanting the n.sup.+ -doped emitter zone with phosphorus, setting a ratio in the n.sup.+ -doped emitter zone between the arsenic dopant concentration and phosphorus dopant concentration to between 10:1 and 500:1, and annealing crystal defects.

Abstract: The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.

Abstract: The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured.