Abstract: A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active region being formed in a direction; gate electrodes of the first and second access transistors crossing the active region, the gate electrodes of the first and second access transistors are parallel with each other; gate electrodes of the first and second drive transistors crossing the active region, the gate electrodes of the first and second drive transistors are parallel with each other, and first and second load devices on the gate electrodes of the first and second access transistors, the first and second load devices are parallel with each other.

Abstract: A semiconductor device includes first and second elements, a light-shielding member, and a comparator. The first and second elements are formed on the same substrate, change in electrical characteristics upon irradiation of ultraviolet rays, and hold the changed states. The first element has the same arrangement as that of the second element. The light-shielding member is formed on the first element to shield ultraviolet rays. The comparator compares the electrical characteristics of the first and second elements and outputs an abnormality detection signal on the basis of the comparison results.

Abstract: In a method of manufacturing a semiconductor device, the InP substrate is subjected to a NH.sub.3 plasma processing by a plasma CVD apparatus into which NH.sub.3 gas is introduced. The InP oxide film is deoxided and removed therefrom and an InN (nitride) film is then formed thereon. S.sub.i H.sub.3 gas and NH.sub.3 gas are introduced into the plasma CVD apparatus to form a SiNx spacer layer on the InN (nitride) film. A source electrode and drain electrode are formed as ohmic electrodes. A Pt layer is stacked on the InP channel region by evaporation lift-off or ion beam sputter method to form a gate electrode. Thereafter, by a process similar to that of forming the SiNx/InN spacer layer, a SiNx/InN passivation film is formed on all over the InP substrate including the source electrode, the drain electrode, and the gate electrode. Accordingly, a semiconductor device protected by the passivation film is completed.

Abstract: Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first conductivity type in the first well region. To improve the electrical characteristics of circuits within the memory device, a first semiconductor device is provided in the first sub-well region (which is biased at a back-bias potential (Vbb)) and a second semiconductor device is provided in the second sub-well region (which is biased at a ground or negative supply potential (Vss)). The first semiconductor device is preferably selected from the group consisting of memory cell access transistors, equalization circuits and isolation gates. The second semiconductor device is also preferably selected from the group consisting of column select circuits and sense amplifiers.

Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Abstract: A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed.

Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction of a diode in a single crystalline substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with most of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and a more stable and conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

Abstract: The structure of a c-axis FEM cell semiconductor includes a silicon substrate; a source junction region and a drain junction region located in the substrate; a gate junction region located between the source junction region and the drain junction region; a FEM gate unit including a lower electrode, a c-axis oriented Pb.sub.5 Ge.sub.3 O.sub.11 FE layer and an upper electrode; wherein the FEM gate unit is sized on the gate junction region such that any edge of said FEM gate unit is a distance "D" from the edges of the source junction region and the drain junction region; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and source, drain and gate electrodes.

Abstract: A semiconductor device comprises a semiconductor acceleration sensor having a cantilever made of a semiconductor material, a supporter for supporting the cantilever, and diffused resistors disposed on the cantilever. An acceleration detecting device detects a displacement of the cantilever based on acceleration forces applied to the cantilever and on changes of resistance values of the diffused resistors.

Abstract: A CCD area sensor comprising two horizontal transfer registers and a charge discharging section comprising a sweep-out electrode adjacent to the side of a horizontal register opposite to an image section and drain section, wherein the horizontal transfer register has a multi-channel structure comprising two transfer channels and a distribution electrode.

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Abstract: An integrated circuit and process for making the same is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, the gate dielectric is formed from a first compound material, and the gate conductor is formed from a second compound material different from the first compound material. Preferably, the gate dielectric is selectively etched such that a portion of the gate conductor extends beyond sidewall surfaces of the gate dielectric, forming a T-shaped gate electrode. In an embodiment, a first ion implantation is used to form lightly doped drain areas aligned with the gate dielectric sidewall surfaces using a large tilt angle implant. Source and drain implant areas are then formed self-aligned with the sidewalls of opposed sidewall spacers using a second ion implant.

Abstract: A semiconductor device having a zener diode, wherein an anode electrode and a cathode electrode of the zener diode have a barrier metal layer as an underlying layer, i.e., a barrier metal structure to simplify manufacturing steps of the semiconductor device, while ensuring that the zener diode is short-circuited with a low resistance without variations in resistance. The anode electrode (6) and the cathode electrode (8) are formed with an underlying metal layer made of a barrier metal. The anode electrode and the cathode electrode are shaped such that Xa<La and Xc<Lc are satisfied, where Xa and Xc are the widths of opposite sides of contact portions of the anode electrode and the cathode electrode, at which they are connected to an anode region and a cathode region, respectively, and La and Lc are the lengths of the respective contact portions.

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

Abstract: An active matrix OED array with an improved device cathode includes a plurality of control transistors formed on a semiconductor substrate with insulating material positioned over the control transistors to form a planar surface. A plurality of contact pads are formed on the planar surface and electrically coupled to the control transistors. A thin (5 .ANG. to 20 .ANG.) electron injecting layer of either alkaline metal oxide or alkaline metal fluoride is positioned on each contact pad and organic material is deposited on the electron injecting layer so as to define an organic light emitting device on each contact pad and electrical and light conducting material is positioned over the organic material to define a second terminal for the OEDs.

Abstract: A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion below the sensing-element portion, in which a removal resistance region having resistance against substrate removal is provided in the silicon substrate between the semiconductor circuit and the cavity portion.

Abstract: A three-dimensional integrated circuit device incorporating any two-dimensional LSIs, such as CCD, MOS-type imaging device and DRAM using trench-type capacitors as its memory cell, can be manufactured economically. Each two-dimensional LSI is prepared by first forming a single-crystal silicon layer on a single-crystal silicon substrate via a porous silicon layer and thereafter forming the two-dimensional LSI on the single-crystal silicon layer. After a support substrate is bonded to the surface of the two-dimensional LSI, the two-dimensional LSI is detached from the single-crystal silicon substrate along the porous layer, and subsequently stacked on another two-dimensional LSI formed on another single-crystal silicon substrate by bonding the bottom surface of the former to the top surface of the latter.

Abstract: This invention provides a semiconductor device such as an MOS transistor and a method of fabricating the same wherein a field oxide film is provided to surround a device region of a semiconductor substrate (including well), providing a gate on the device region via a gate insulating film, forming main doped layers destined to become a source and a drain in the device region of the semiconductor substrate between the gate and the field oxide film on opposite sides of the gate, and providing main active layers (high-concentration diffusion layers) having the impurity diffused and activated therein. Sub-doped layers are formed by selectively adding impurity to regions of the semiconductor substrate at boundaries between the device region and the field oxide film (except in the vicinity of the gate) and sub-active layers having the impurity diffused and activated therein are provided.