Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.

Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

Abstract: A molecular scrivener reads data from or writes data to a macromolecule and includes: a pair of shielding electrodes; a scrivener electrode between the first and second shielding electrodes and that electrically floats at a third potential that, in an absence of a charged or dipolar moiety of the macromolecule, is intermediate between the first and second potentials and changes in a presence of the charged or dipolar moiety; a dielectric layer interposed between shielding electrodes and the scrivener electrode; and a nanopore that communicates the macromolecule through the electrodes and dielectric layers. Reading data from or writing data to a macromolecule includes: sequentially receiving, at the scrivener electrode, individual moieties of the macromolecule so that the third potential responds to individual moieties; communicating the macromolecule from the scrivener electrode to the second shielding electrode and from second shielding electrode to expel the macromolecule from the nanopore.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Abstract: A memory device includes a memory cell array, a current detector and a controller. The memory cell array has a plurality of memory cell strings coupled to a common source line. The current detector detects a circulating current on the common source line or a power end of a page buffer. The controller is configured to: during a program operation, perform a first program operation on a plurality of first memory cells corresponding to logic 0 according to a first program verify voltage, and perform a second program operation on a plurality of second memory cells corresponding to logic 1 according to a second program verify voltage, where the first program verify voltage is different from the second program verify voltage; and provide a read voltage to the memory cell strings during a read operation, and sense the circulating current based on a read current reference value.

Abstract: An operating method for a non-volatile memory device includes; performing a read operation on adjacent memory cells connected to an adjacent word line proximate to a target word line to determine adjacent data, classifying target memory cells connected to the target word line into groups according to the adjacent data, setting a read voltage level for each of the groups by searching for a read voltage level for target memory cells in at least one of the groups, and performing a read operation on target memory cells using the read voltage level set for each of the groups.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Abstract: The present technology relates to an electronic device. A memory device that reduces noise generated during a sensing operation includes a plurality of pages, each including a plurality of memory cells, a peripheral circuit configured to sense a selected page among the plurality of pages, the selected page including a selected memory cell and a sensing node controller configured to control, based on a result of a first sensing operation among a plurality of sensing operations that are performed to sense a logical page among a plurality of logical pages in the selected page, a sensing node in a page buffer coupled to the selected memory cell through a bit line during a second sensing operation.

Abstract: A memory device according to an embodiment includes a plurality of cell strings each including a select transistor and memory cells connected in series, a peripheral circuit configured to apply a verify voltage to the select transistor and perform an internal operation on the memory cells, and control logic configured to control the peripheral circuit to apply an operation voltage for the internal operation. The control logic includes a bad string management component configured to verify threshold voltages of the select transistor and control the peripheral circuit to perform the internal operation on a cell string including a select transistor passed in verification according to a verify result of the select transistor.

Abstract: A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

Abstract: A memory device and a method of correcting error in a memory device is provided. The memory device controller includes a memory array, a tie-breaker array, a write controller, a verify circuit, and a controller. The memory array includes a plurality of memory cells. The tie-breaker array includes a plurality of tie-breaker rows. The write controller is configured to apply a programming voltage to the memory array. The verify circuit is configured to apply a verify voltage to verify whether the memory cells in the memory array are in an unambiguous state or not. The controller is configured to enable one or more tie-breaker rows in additions to the memory array to adjust an output of the memory array when the memory cells in the memory array are in an ambiguous state.

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

Abstract: Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.