Patents Examined by Xiaoliang Chen
  • Patent number: 11612064
    Abstract: A component carrier includes (a) a first stack with at least one first electrically conductive layer structure and/or at least one first electrically insulating layer structure; (b) a hole formed within the first stack; and (c) a non-deformable solid body closing a portion of the hole and being spaced with respect to side walls of the hole by a gap. A component carrier assembly includes (a) a component carrier as described above; (b) a second stack having at least one second electrically conductive layer structure and/or at least one second electrically insulating layer structure; and (c) a connection piece connecting the first stack with the second stack. Further described are methods for manufacturing such a component carrier and such a component carrier assembly.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 21, 2023
    Assignee: AT&SAustria Technologie & Systemtechnik AG
    Inventors: Erich Schlaffer, Markus Steinkellner
  • Patent number: 11610724
    Abstract: A coil component includes a support substrate, a first coil and a second coil disposed on the support substrate to be spaced apart from each other, and a body including a first core and a second core penetrating through the first coil portion and the second coil portion and spaced apart from each other. The first coil portion has a first winding portion, forming at least one turn about the first core, and a first extension portion extending from one end portion of the first winding portion to surround the first core and the second core. The second coil has a second winding portion, forming at least one turn about the second core, and a second extension portion extending from one end portion of the second winding portion to surround the first core and the second core. A separation distance between a given turn of the first coil portion and an adjacent turn of the second coil portion is different from a separation distance between adjacent turns of the first coil portion.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 21, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Hyuk Jung, Young Sun Kim, Sung Hee Kim
  • Patent number: 11596060
    Abstract: A display unit includes a display panel, a circuit board bent from a front surface of the display panel toward a rear surface of the display panel, a window disposed on the front surface of the display panel to cover an active area, and a cover panel film disposed on the rear surface of the display panel and disposed between the display panel and the circuit board. The cover panel film includes a first portion overlapping with the display panel, and a second portion extending from the first portion to protrude from the display panel when viewed in a plan view. The second portion is disposed between the circuit board and the window when viewed in a cross-sectional view.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 28, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Soo Han, Hwa-Su Lim
  • Patent number: 11590719
    Abstract: A fiber-composite part having one or more electronic components that are located in arbitrary regions of the internal volume of the part are fabricated using a preform charge. The preform charge has a structure that corresponds to that of the mold cavity in which the part is being formed. By incorporating the electronic components in the preform charge, such components are then precisely located, spatially oriented, and constrained, and such location and orientation is maintained during molding to produce a part with the electronic components in the desired locations and orientations within its internal volume.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 28, 2023
    Assignee: Arris Composites Inc.
    Inventors: Ethan Escowitz, Riley Reese, J. Scott Perkins, Erick Davidson
  • Patent number: 11589464
    Abstract: A electronic component including a first protective layer covering the substrate and the conductive tract, a second protective layer covering at least a portion of the first protective layer, wherein the second protective layer includes Parylene, and a third protective layer covering at least a portion of the second protective layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: February 21, 2023
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Haralambos Cordatos, Xin Wu, Peter J. Walsh, Parag M. Kshirsagar
  • Patent number: 11582865
    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 14, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11582871
    Abstract: A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 14, 2023
    Assignees: Hong Heng Sheng Electronical Technology (HuaiAn) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Pan Tang, Fu-Lin Chang
  • Patent number: 11565825
    Abstract: Multifunctional surfacing materials for use in composite structures are disclosed. According to one embodiment, the surfacing material includes (a) a stiffening layer, (b) a curable resin layer, (c) a conductive layer, and (d) a nonwoven layer, wherein the stiffening layer (a) and the nonwoven layer (d) are outermost layers, and the exposed surfaces of the outermost layers are substantially tack-free at room temperature (20° C. to 25° C.). The conductive layer may be interposed between the curable resin layer and the stiffening layer or embedded in the curable resin layer. According to another embodiment, the surfacing material includes a fluid barrier film between two curable resin layers. The surfacing materials may be in the form of a continuous or elongated tape that is suitable for automated placement.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 31, 2023
    Assignee: CYTEC INDUSTRIES INC.
    Inventors: Junjie Jeffrey Sang, Dalip Kumar Kohli, Kevin R. Mullery
  • Patent number: 11570908
    Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 31, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: Steve M. Wilkinson, Daniel J. Prezioso
  • Patent number: 11553589
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 10, 2023
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 11553599
    Abstract: A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: January 10, 2023
    Assignee: AT&S(Chongqing) Company Limited
    Inventor: Yu-Hui Wu
  • Patent number: 11551864
    Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 11546990
    Abstract: A component carrier with an electrically insulating layer structure has opposed main surfaces, a through-hole, and an electrically conductive bridge structure connecting opposing sidewalls delimiting the through-hole. The sidewalls have a first tapering portion extending from a first main surface and a second tapering portion extending from a second main surface. A first demarcation surface faces the first main surface and a second demarcation surface faces the second main surface. A central bridge plane extends parallel to the first main surface and the second main surface and is at a vertical center between a lowermost point of the first demarcation surface and an uppermost point of the second demarcation surface. A first intersection point is between the central bridge plane and one of the sidewalls delimiting the through hole. A length of a shortest distance from the first intersection point to the first demarcation surface is at least 8 ?m.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 3, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Mikael Tuominen
  • Patent number: 11546988
    Abstract: A display device includes a display panel, a printed circuit board attached to the display panel and including a ground potential supply terminal, a circuit, and a wiring pattern electrically coupling the ground potential supply terminal and the circuit, and a housing that contacts a coupling place provided to the wiring pattern and is attached to the printed circuit board through the coupling place. The wiring pattern includes a terminal wiring pattern electrically coupled with the ground potential supply terminal, a circuit wiring pattern branched from a branch part at a predetermined position on the terminal wiring pattern and electrically coupled with the circuit, and a housing wiring pattern branched from the branch part of the terminal wiring pattern and electrically coupled with the coupling place, and the circuit wiring pattern and the housing wiring pattern are uncoupled with each other at any place other than the branch part.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: January 3, 2023
    Assignee: Japan Display Inc.
    Inventor: Kohei Kinoshita
  • Patent number: 11546974
    Abstract: The present invention provides a conductive fabric comprising base cloth and a conductive metallic circuit structure formed on the surface of the base cloth. The conductive metallic circuit structure comprises at least one metallic seed layer and at least one chemical-plating layer. The metallic seed layer is an evaporation-deposition layer or a sputter-deposition layer and has a circuit pattern. The chemical-plating layer is applied over the surface of the metallic seed layer. The conductive fabric has improved conductivity and heat generation efficiency.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: January 3, 2023
    Assignee: FORMOSA TAFFETA CO., LTD.
    Inventors: Fang-Jong Liu, Hsing-Nan Chung, Meng-Yueh Wu
  • Patent number: 11538887
    Abstract: A display device includes: a display substrate including a display area and a pad area disposed around the display area; a signal wiring disposed over the display area and the pad area on the display substrate; at least one wiring pad including: a pad pattern portion disposed on the pad area of the display substrate and electrically connected to the signal wiring; and a separation pattern portion separated from the pad pattern portion by a separation space; and a printed circuit board attached to the pad area of the display substrate, the printed circuit board including a lead wiring connected to the at least one wiring pad.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 27, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Man Bae, Se Hun Park, Chang Mo Park, So Yeon Joo
  • Patent number: 11540396
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: December 27, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shao-Chien Lee, John Hon-Shing Lau, Chen-Hua Cheng, Ra-Min Tain
  • Patent number: 11526718
    Abstract: A mini smart card and a method of manufacturing the mini smart card are introduced. The method includes disposing bilayered print layers on a top side and a bottom side of a circuit layer, respectively; performing a heat-compression treatment and then a printing treatment on the circuit layer and the bilayered print layers; removing surface layers from the bilayered print layers; and disposing transparent protective layers on the bilayered print layers, respectively. The bilayered print layers are prevented from deforming under the heat generated during the printing treatment. Removal of the surface layers from the bilayered print layers effectively reduces the thickness of the mini smart card.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: December 13, 2022
    Assignee: BEAUTIFUL CARD CORPORATION
    Inventor: Meng-Jen Cheng
  • Patent number: 11528810
    Abstract: A wiring board includes: an insulating layer; and a connection terminal formed on the insulating layer. The connection terminal includes a first metal layer laminated on the insulating layer, a second metal layer laminated on the first metal layer, a metal pad laminated on the second metal layer, and a surface treatment layer that covers an upper surface and a side surface of the pad and that is in contact with the upper surface of the insulating layer. An end portion of the second metal layer is in contact with the surface treatment layer, and an end portion of the first metal layer is positioned closer to a center side of the pad than the end portion of the second metal layer is to form a gap between the end portion of the first metal layer and the surface treatment layer.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: December 13, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yoko Nakabayashi, Yuta Sakaguchi
  • Patent number: 11523518
    Abstract: According to an aspect of the present disclosures, a method of making a flexible printed circuit board, which includes a base film having an insulating property, a conductive pattern disposed on either one or both surfaces of the base film, and a cover layer covering a conductive-pattern side of a laminated structure inclusive of the base film and the conductive pattern, includes a superimposing step of superimposing a cover film on the conductive-pattern side of the laminated structure, the cover film having a first resin layer and a second resin layer that is laminated to an inner side of the first resin layer and that softens at a lower temperature than does the first resin layer, and a pressure bonding step of vacuum bagging the laminated structure and the cover film at a temperature higher than a softening temperature of the second resin layer.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: December 6, 2022
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kou Noguchi, Hiroshi Ueda