Abstract: Disclosed is an electronic device comprising: a connection circuit configured to provide an electrical connection of an external power supply device; a processor electrically connected to the connection circuit; a memory operatively connected to the processor; and a reset circuit electrically connected to the connection circuit and operatively connected to the processor. The processor is configured to” transmit, to the reset circuit, an interrupt signal during a first time at least partially based on the identification of the connecting to the external power supply device through the connection circuit, and the reset circuit may be configured to: determine whether the interrupt signal is received within a second time after the connecting to the external power supply device through the connection circuit, and transmit, to the processor, a reset signal for a hardware reset of the processor based on the interrupt signal not being received within the second time.

Abstract: Methods and apparatus to manage power and performance of computing devices based on user presence are disclosed. An apparatus includes an engagement detector to determine an engagement of a user with a device based on at least one of image data generated by an image sensor or an application running on the device; and an operation mode selector to select one of a plurality of operation modes for the device based on a level of engagement of the user, the plurality of operation modes including (1) a first operation mode associated with the device operating at a first performance level and a first power level and (2) a second operation mode associated with the device operating at a second performance level and a second power level, the first performance level being higher than the second performance level, the first power level being higher than the second power level.

Abstract: A secure Basic Input/Output System (BIOS)-enabled passthrough system includes a computing device having a computing device component, and a BIOS subsystem in the computing device that is coupled to the computing device component. The BIOS subsystem enables primary access to the computing device component to BIOS drivers. The BIOS subsystem may receive a secondary access session start request from a first BIOS driver to start a secondary access session to use secondary access to the computing device component, it retrieves a first BIOS driver identifier for the first BIOS driver based on the secondary access session start request, determines that the first BIOS driver identifier is a secondary-access-authorized BIOS driver identifier and, in response, begins the first secondary access session and may performs secondary access operation(s) on the computing device component in response to receiving secondary access command(s) from the first BIOS driver during the secondary access session.

Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: In general, embodiments of the invention relate to implementing a secure boot process in information handling systems that supports both an external root of trust (eRoT) and an internal root of trust (RoT). Further, embodiments of the invention relate to binding a management controller to a specific chassis and, in the case where the eRoT is used, to an eRoT. When the management controller and the chassis are provisioned according to one or more embodiments of the invention, security checks may be performed by management controller executing an initial program loader (IPL) using the aforementioned bindings. If the bindings are not present or do not match, then the boot process halts and the user is unable to use the information handling system.

Abstract: The architecture includes four largely independent subsystems which are arranged hierarchically and each form an isolated Fault-Containment Unit (FCU). At the top of the hierarchy is a secure subsystem, the Fault-Tolerant Decision Subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are insecure because they contain complex software executed on non-fault-tolerant hardware. Experience has shown that it is difficult to find all design errors in a complex software system and to prevent an intrusion. The redundancy and diversity inherent in this architecture masks every error—even a Byzantine error—of an insecure subsystem in such a way that no safety-critical failure can occur.

Abstract: An operating method of a power optimization scheduler is provided, where the operating method of a power optimization scheduler includes obtaining information regarding a neural network (NN) model, determining a voltage value for a task to be performed by at least one processing device, based on the obtained information regarding the NN model, and controlling a power management device to apply a voltage corresponding to the determined voltage value to the at least one processing device.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: During a power-on self-test (POST), a basic input/output system (BIOS) retrieves an attribute value associated with the persistent memory device, and compares the attribute value to a default value. In response to the attribute value matching the default value, the BIOS may determine that a firmware management protocol was not executed during a previous POST. In response to the attribute value not matching the default value, the BIOS may compare the attribute value to a current firmware version of firmware within the persistent memory device.

Abstract: A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.

Abstract: A semiconductor device includes: a plurality of cores configured to receive power from a power supply; a plurality of power switch circuits provided for each core and configured to control the power supplied to the corresponding cores; a compare circuit configured to receive power from the power supply and compare output data of the plurality of cores; and a core voltage monitor circuit configured to monitor a voltage of a node that connects the power supply and the compare circuit.

Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for monitoring a parameter of one or more of the hardware devices of the IHS when a custom BMC firmware stack is executed on the BMC. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. When the parameter exceeds a specified threshold, the instructions are further executed to control the BMC to perform one or more operations to remediate the excessive parameter.

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

Abstract: A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

Abstract: The invention is part of the field of computer technology. It describes the architecture of a secure automation system and a method for safe autonomous operation of a technical apparatus, in particular a motor vehicle. The architecture disclosed herein solves the problem that any Byzantine error in one of the complex subsystems of a distributed real-time computer system, regardless of whether the error was triggered by a random hardware failure, a design error in the software or an intrusion, must be recognized and controlled in such a way that no security-relevant incident occurs. The architecture includes four largely independent subsystems which are arranged hierarchically and each form an isolated Fault-Containment Unit (FCU). At the top of the hierarchy is a secure subsystem, which executes simple software on fault-tolerant hardware. The other three subsystems are insecure because they contain complex software executed on non-fault-tolerant hardware.

Abstract: There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

Abstract: A controller and techniques for expanding its feature capabilities. Techniques may incorporate using an external memory to store feature sets that can be downloaded to an internal memory for intimate incorporation and usage by the controller. The external memory may be large in comparison to the internal memory. External storage of additional feature sets allows for use of a small and simple controller with access to numerous feature sets that otherwise could not be incorporated by the small controller.

Abstract: Scalable life-cycle maintenance of hardware. In an embodiment, a software-defined Preboot eXecution Environment (PXE) server is executed to receive a request, comprising an identifier, from hardware. The identifier is compared to a plurality of attribute sets. When the identifier does not match any of the attribute sets, a task graph is generated for a PXE process for the hardware, and an initial stage of the task graph is initiated. Otherwise, when the identifier matches one of the attribute sets, the task graph associated with that attribute set is retrieved, and the next stage in the task graph is initiated. In addition, a display key may be used to tether hardware with a user system. Furthermore, hardware may be validated by comparing signatures using a validating operating system, and a boot order of operating systems in the hardware may be changed once the hardware device is validated.