Patents by Inventor A. Purushotham

A. Purushotham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Embedded memory testing using back-to-back write/read operations
    Patent number: 9728273
    Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 8, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kanad Chakraborty, Naveen Purushotham
  • PROCESS OF MANUFACTURING HIGH QUALITY COMPOSITE MATERIALS USING AN ISO-STATIC HIGH PRESSURE REACTOR
    Publication number: 20170190163
    Abstract: A process of bonding different constituent materials of different tensile strengths in a single step in an isostatic high pressure reactor in order to produce a composite material.
    Type: Application
    Filed: June 30, 2015
    Publication date: July 6, 2017
    Inventor: Purushotham Mahavadi
  • Techniques for rapid deployment of service artifacts
    Patent number: 9690557
    Abstract: A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: June 27, 2017
    Assignee: Oracle International Corporation
    Inventors: Arvind Srinivasamoorthy, Purushotham Kola, Ravindran Sankaran, Annaji Garimella, Raghavateja Kalapatapu, Thirupathi Reddy Annadi, Mark James Glenn Craig, Nan Xie
  • SAFELY FACILTATING HIGHER RISK PAYMENTS
    Publication number: 20170154324
    Abstract: A method of facilitating e-commerce and/or contactless payments funded by a funding account that is blocked from directly making such payments, said method comprising a virtual card interface computing system, comprising an application running on a user device and a server: storing details to link a virtual card (VC) account with said funding account at said server; receiving an instruction from a user of said VC account through said application to transfer funds from the funding account to the VC account; and initiating requesting said transfer from an issuer of the funding account. Also, a method of making an e-commerce or contactless payment funded by a funding account that is blocked from directly making such payments comprising: funding a VC account according to the aforementioned method; and subsequently making said payment by providing VC credentials of the VC account to a payee.
    Type: Application
    Filed: November 23, 2016
    Publication date: June 1, 2017
    Inventors: Karan Singh, Vikram Jammihal, Sanjiv Purushotham, Hassan Akbar, Sumit Mittal
  • Processor performance monitoring unit synchronization
    Patent number: 9626229
    Abstract: A method for monitoring performance of events occurring in a multiprocessor system is provided where the performance monitoring units (PMUs) are globally synchronized. The global synchronization is carried out with a dedicated bit field set to any of pause, stop, restart, or reset command. The command is sent across the scan communications interface (SCOM) of all chips by using existing fabric connecting all nest units to control the PMUs in the system. A pre-scale counter before a main counter may be used to buffer event counts until a reset or a restart command is sent to the SCOM in the system.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Krolak, Charles F. Marino, Sooraj R. Nair, Srinivas Purushotham, Srinivasan Ramani
  • Device, system and method for alignment of an integrated circuit assembly
    Patent number: 9625256
    Abstract: Techniques and mechanisms for evaluating misalignment of circuit structures. In an embodiment, infrared (IR) radiation is variously focused on different planes of an assembly including an integrated circuit (IC) chip and a substrate that is to be coupled to, or that is coupled to, the IC chip. The cross-sectional planes include respective structures that variously reflect IR radiation. The reflected IR radiation is measured to create images each representing a corresponding cross-section of the assembly. In another embodiment, respective reference features of the images are identified and evaluated to determine whether a misalignment between the reference features satisfies one or more threshold test conditions.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Purushotham Kaushik Muthur Srinath, Mario Pacheco, Deepak Goyal
  • Digital link viewer with paging for super-channels
    Patent number: 9608866
    Abstract: A device may receive optical network information associated with a plurality of super-channels. Each super-channel, of the plurality of super-channels, may include a plurality of optical channels transported as a single optical channel. The device may assign the plurality of super-channels to a plurality of sets of super-channels. The device may receive a request for a subset of the optical network information associated with a set of super-channels of the plurality of sets of super-channels. The device may provide, based on the request, information that identifies the subset of the optical network information associated with the set of super-channels via a user interface.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: March 28, 2017
    Assignee: Infinera Corporation
    Inventors: Karthikeyan Mathruboodham Nagarajan, Naveen Narasimha Hegde, Vinesh Raghavan, Purushotham Pururava Pushpavanth, Musab Qamri
  • MEMORY ACTIVITY DRIVEN ADAPTIVE PERFORMANCE MEASUREMENT
    Publication number: 20170060476
    Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
  • MEMORY ACTIVITY DRIVEN ADAPTIVE PERFORMANCE MEASUREMENT
    Publication number: 20170060423
    Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
    Type: Application
    Filed: November 5, 2015
    Publication date: March 2, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
  • DIGITAL LINK VIEWER WITH PAGING FOR SUPER-CHANNELS
    Publication number: 20170033999
    Abstract: A device may receive optical network information associated with a plurality of super-channels. Each super-channel, of the plurality of super-channels, may include a plurality of optical channels transported as a single optical channel. The device may assign the plurality of super-channels to a plurality of sets of super-channels. The device may receive a request for a subset of the optical network information associated with a set of super-channels of the plurality of sets of super-channels. The device may provide, based on the request, information that identifies the subset of the optical network information associated with the set of super-channels via a user interface.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 2, 2017
    Inventors: Karthikeyan Mathruboodham NAGARAJAN, Naveen Narasimha HEGDE, Vinesh RAGHAVAN, Purushotham Pururava PUSHPAVANTH, Musab QAMRI
  • HOST MANAGEMENT ACROSS VIRTUALIZATION MANAGEMENT SERVERS
    Publication number: 20160380832
    Abstract: In an example, method of managing hosts across a plurality of virtualization management servers, each of the plurality of virtualization management servers managing a plurality of the hosts, each of the hosts configured with virtualization software executing at least one virtual computing instance is disclosed.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 29, 2016
    Inventors: RUPESH PURUSHOTHAM, RAM PRAKASH SONI, SHWETHA LAKSHMAN RAO
  • Dynamic prescaling for performance counters
    Patent number: 9515663
    Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
  • Compositions that Inhibit and Prevent the Formation of Dental Caries and Methods of Using the Same
    Publication number: 20160331662
    Abstract: The present invention is related to the inhibition of binding of oral streptococci to the tooth surface. Compositions and methods for preventing, inhibiting and/or treating the formation of dental caries, and methods of identifying compounds that prevent, inhibit and/or treat the formation of dental caries are provided.
    Type: Application
    Filed: January 9, 2015
    Publication date: November 17, 2016
    Applicant: UAB Research Foundation
    Inventors: Champion Deivanayagam, Sangeetha Purushotham
  • DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS
    Publication number: 20160294396
    Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
    Type: Application
    Filed: June 14, 2016
    Publication date: October 6, 2016
    Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
  • Knowledge Based Factorized High Order Sparse Learning Models
    Publication number: 20160259887
    Abstract: An optimization-driven sparse learning framework is disclosed to identify discriminative system components among system input features that are essential for system output prediction. In biomarker discovery, to handle the combinatorial interactions among gene or protein expression measurements for identifying interaction complexes and disease biomarkers, the system uses both single input features and high-order input feature interactions.
    Type: Application
    Filed: February 22, 2016
    Publication date: September 8, 2016
    Inventors: Renqiang Min, Sanjay Purushotham
  • Dynamic prescaling for performance counters
    Patent number: 9419625
    Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
  • Techniques for automated generation of service artifacts
    Patent number: 9395965
    Abstract: A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: July 19, 2016
    Assignee: Oracle International Corporation
    Inventors: Annaji Garimella, Nan Xie, Ravindran Sankaran, Thirupathi Reddy Annadi, Arvind Srinivasamoorthy, Purushotham Kola, Mark James Glenn Craig
  • DYNAMIC PRESCALING FOR PERFORMANCE COUNTERS
    Publication number: 20160065219
    Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani
  • Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures
    Patent number: 9230833
    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
  • Embedded Memory Testing Using Back-To-Back Write/Read Operations
    Publication number: 20150340103
    Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: Lattice Semiconductor Corporation
    Inventors: Kanad Chakraborty, Naveen Purushotham