Abstract: In certain embodiment, built-in self-test (BIST) circuitry for multiport memory comprises a configurable address generator and a configurable data generator. The configurable address generator can be configured to concurrently generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for any selected memory mode of a plurality of available memory modes having different column-multiplexing schemes. The configurable data generator can be configured to concurrently generate two sets of data for the selected memory mode, such that (i) the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address and (ii) the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address. The BIST circuitry enables efficient, physically aware built-in self-testing.

Abstract: A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a

Abstract: A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a

Abstract: A system for resubmitting a message for integration of applications receives information relating to a plurality of messages. Each message of the plurality of messages has been unsuccessfully transmitted between integration milestones, the message for resubmission being one of the plurality of messages. The corresponding integration milestones of the plurality of messages comprise different types of integration milestones. The system receives criteria to filter the received information. The system determines the message for resubmission by filtering the received information in accordance with the received criteria. The system sends the message from a first integration milestone to a second integration milestone.

Abstract: An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Abstract: A method and system that allows multiple developers to collaborate together by developing, modifying and sharing code components and data which are integrated to provide a solution to a computational problem. The system enforces a sharing mechanism for the components (code and data) and an interface between components. The system allows developers to execute the components either locally or remotely. The system determines a consumption metric based on the resource consumption of each component (compute/storage/bandwidth). The system determine a contribution metric for each developer's components to the overall solution.

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract: A network based positioning (NBP) system is disclosed that allows any of its access points (APs) to initiate ranging operations with a station device (STA), regardless of whether the STA is in power save mode and regardless of whether a particular AP is currently associated with the STA. For example, to initiate ranging operations with the STA from a non-associated AP, the non-associated AP obtains the TSF timer of the associated AP, and then uses the obtained TSF timer to derive the associated AP's beacon transmission schedule and thereby determine when the STA's corresponding wake-up periods occur. Thereafter, the non-associated AP can initiate ranging operations with the STA during the STA wake-up periods, thereby ensuring that probes sent from the non-associated AP will arrive at the STA while the STA is awake from power save mode.

Abstract: A wireless network is disclosed that allows an access point (AP) to keep a station (STA) in an awake state for an extended duration by periodically sending “keep-awake” frames to the STA. The keep-awake frames may be NULL frames having an asserted “more data” bit. For some embodiments, the AP transmits a beacon frame to the STA, wherein the beacon frame includes an asserted traffic indication bit that causes the STA to remain in the awake state for an additional wake-up period. Then, the AP transmits a sequence of keep-awake frames to the STA, wherein each keep-awake frame causes the STA to remain in the awake state for an additional time period.

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract: A system for resubmitting a message for integration of applications receives information relating to a plurality of messages. Each message of the plurality of messages has been unsuccessfully transmitted between integration milestones, the message for resubmission being one of the plurality of messages. The corresponding integration milestones of the plurality of messages comprise different types of integration milestones. The system receives criteria to filter the received information. The system determines the message for resubmission by filtering the received information in accordance with the received criteria. The system sends the message from a first integration milestone to a second integration milestone.

Abstract: A system that drives multiple MOSFETs in parallel for direct current and alternating current solid state power controller applications may include networks connected to the gates of the MOSFETs to protect the MOSFETs from being damaged during high current interruption. For direct current applications, the system may include a switching protection and damping network and a gate drive balancing network. For alternating current applications, the system may include two switching protection and damping networks and a gate drive balancing network.

Abstract: Methods, computer readable media, and apparatuses for analyzing data quality are presented. Transaction information may be received from a database, and the transaction information may describe various aspects of a plurality of transactions handled by an organization. Subsequently, a forecast may be calculated based on the transaction information, and the forecast may predict the future value of a metric. An upper control limit and a lower control limit for the metric may be determined based on the transaction information. Thereafter, the latest actual value of the metric may be computed. A normalized quality score for the metric then may be calculated based on the latest actual value of the metric, the forecast, the upper control limit, and the lower control limit. Optionally, a chart may be generated to evaluate data quality for a plurality of metrics, and metrics that exceed a control limit may be added to an issue log.

Abstract: An active patch panel uses small form factor plus (SFP+) connectivity with a plurality of channels extending between first and second faces of the panel. The channels connect ports on the opposing faces of the panel and are provided with additional electronic elements, such as an equalizer, a clock data recovery element, and a pre-emphasis element. A controller can be connected to the plurality of channels to provide instructions for simultaneous equalization and pre-emphasis of a plurality of cable assemblies in the same channel.

Abstract: Pre-charge circuitry allows capacitive loads connected to a solid state power controller to be gradually charged up by a PWM, generated with a cycle by cycle current limit, switching a single MOSFET in series with an inductor, before the SSPC is turned on. The pre-charge circuitry may require only three additional components, e.g., a MOSFET, an inductor and a diode, along with a designated MOSFET gate driver.

Abstract: A power distribution system includes the use of a master digital signal processor (DSP) and two slave DSPs connected to the master DSP. The slaves DSPs may be connected to each of a plurality of solid state power channels (SSPC) controlling power distribution functions to each of the channels. A power control strategy may use one power supply for the master DSP, a second power supply shared between the slave DSPs, and a third power supply shared between each of the SSPC channels.

Abstract: A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables.

Abstract: A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables.

Abstract: A method and formulation for drinking water with herbal hint, in particular for packaged drinking water with herbal hint, is provided. The formulation includes water, wherein the water satisfies the pre-specified standards of drinking water. Further, the formulation includes one or more herbal ingredients. Also, the formulation includes essential oil of Rosemary to stabilize the formulation and hence to increase its shelf life.

Abstract: A network based positioning (NBP) system is disclosed that allows any of its access points (APs) to initiate ranging operations with a station device (STA), regardless of whether the STA is in power save mode and regardless of whether a particular AP is currently associated with the STA. For example, to initiate ranging operations with the STA from a non-associated AP, the non-associated AP obtains the TSF timer of the associated AP, and then uses the obtained TSF timer to derive the associated AP's beacon transmission schedule and thereby determine when the STA's corresponding wake-up periods occur. Thereafter, the non-associated AP can initiate ranging operations with the STA during the STA wake-up periods, thereby ensuring that probes sent from the non-associated AP will arrive at the STA while the STA is awake from power save mode.