Patents by Inventor A. Purushotham

A. Purushotham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10135692
    Abstract: In an example, method of managing hosts across a plurality of virtualization management servers, each of the plurality of virtualization management servers managing a plurality of the hosts, each of the hosts configured with virtualization software executing at least one virtual computing instance is disclosed. The method includes deploying, by a rescue service, a rescue agent on each of the plurality of virtualization management servers; obtaining host inventories and configurations at the rescue service for the plurality of virtualization management servers; assigning each of the plurality of virtualization management servers to a category of a plurality of categories based on configuration maximums of the plurality of virtualization management servers; and updating rescue storage managed by the rescue service to monitor resource usage of the plurality of virtualization management servers based on assigned category and the host inventories.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 20, 2018
    Assignee: VMware, Inc.
    Inventors: Rupesh Purushotham, Ram Prakash Soni, Shwetha Lakshman Rao
  • Patent number: 10127131
    Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sooraj R. Nair, Srinivas Purushotham, Madhavan Srinivasan
  • Publication number: 20180283845
    Abstract: An interferometer for characterizing a sample, the interferometer including a light emitter to produce a light beam. A wavelength modulator can dither a wavelength of the light beam to produce an input beam having an oscillating wavelength. A beam splitter can be configured to divide the input beam into a reference beam and a measurement beam. The reference beam can reflect from a mirror having a fixed position and return to the beam splitter. The measurement beam can reflect from the sample and return to the beam splitter. The beam splitter can interfere the received reference beam and measurement beam to form an output beam. A detector can convert the output beam to an electrical signal. A processor can control the wavelength modulator, receive the electrical signal, and determine a distance to the sample based on the electrical signal and the oscillating wavelength of the input beam.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Mario Pacheco, Manish Dubey, Purushotham Kaushik Muthur Srinath, Deepak Goyal, Liwen Jin
  • Patent number: 10078447
    Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
  • Publication number: 20180259547
    Abstract: In an embodiment, an ice-prevention dam for a pitot tube includes a body and a head. The body includes a notch having a substantially planar back, and the head extends from the body and has a substantially planar side that is substantially parallel to the back of the notch. Such a dam can prevent ice accumulation in a pitot tube, and can facilitate proper positioning of the dam. For example, during manufacture of a pitot tube, an assembler inserts the dam into a hole in a side of a pitot-tube body having a front opening such that the head of the dam is located outside of the pitot-tube body and a body of the dam is located inside of the pitot-tube body. Next, the assembler positions the dam by causing the substantially planar side of the dam head to be substantially parallel with the front opening of the pitot-tube body.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: Sadique Mohammad Abdullah, Purushotham Reddy B., Narasimha Reddy Venkatarayappa, Murali Krishnan Payangapadan, Eswara Naidu Chikkala, Rama Sateesh Venkata Kandula
  • Publication number: 20180254256
    Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).
    Type: Application
    Filed: September 25, 2015
    Publication date: September 6, 2018
    Inventors: Pilin Liu, Purushotham Kaushik Muthur Srinath, Deepak Goyal
  • Patent number: 10067672
    Abstract: A method of monitoring memory performance comprises selecting a first portion of memory from two or more portions of memory in accordance with an adaptive mode indicated by configuration bits in a control register; monitoring memory accesses to the selected portion of memory during a first sampling period; selecting a different portion of memory from the two or more portions of memory in accordance with the adaptive mode for monitoring the different portion of memory in a subsequent sampling period; monitoring memory accesses to the different portion of memory during the subsequent sampling period; recording a respective number of memory accesses for each portion of memory over a plurality of sampling periods; and generating one or more interrupts to output data regarding the monitored memory accesses for data analysis.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Srinivas B. Purushotham
  • Publication number: 20180182140
    Abstract: The systems may include superimposing a canvas layer having a pixel system over the digital map; aligning the coordinate system of the digital map with the pixel system of the canvas layer; obtaining a location coordinate of the coordinate system to each site of interest of a plurality of sites of interest, wherein the location coordinate is associated with a location of the site of interest on the digital map; associating the location coordinate for the site of interest with a pixel in the pixel system; and creating a marker on the canvas layer on the pixel associated with the location coordinate for the site of interest.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Applicant: American Express Travel Related Services Company, Inc.
    Inventors: Kedar Biradar, Raju Rathi, Kunal Upadhyay, Purushotham Vunnam, Digvijay Yadav
  • Publication number: 20180181806
    Abstract: The systems may include dividing a digital map provided by a mapping system into a matrix having a plurality of cells; assigning a cell of the plurality of cells to encompass a geographic region of the digital map; calculating a number of sites of interest in the cell; creating a marker comprising a first count number representing the number of sites of interest in the cell; and sharing the marker with a browser for display on the digital map.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Applicant: American Express Travel Related Services Company, Inc.
    Inventors: Shivakumar Chandrashekar, Raju Rathi, Yogesh Tayal, Kunal Upadhyay, Purushotham Vunnam
  • Publication number: 20180158552
    Abstract: A method for creating an interpretable model for healthcare predictions includes training, by a deep learning processor, a neural network to predict health information by providing training data, including multiple combinations of measured or observed health metrics and corresponding medical results, to the neural network. The method also includes determining, by the deep learning processor and using the neural network, prediction data including predicted results for the measured or observed health metrics for each of the multiple combinations of the measured or observed health metrics based on the training data. The method also includes training, by the deep learning processor or a learning processor, an interpretable machine learning model to make similar predictions as the neural network by providing mimic data, including combinations of the measured or observed health metrics and corresponding predicted results of the prediction data, to the interpretable machine learning model.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 7, 2018
    Inventors: Yan Liu, Zhengping Che, Sanjay Purushotham
  • Publication number: 20180155393
    Abstract: The present disclosure relates to methods for making asunaprevir, useful treatment of Hepatitis C virus (HCV) infection, and its intermediates.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 7, 2018
    Inventors: Scott A. SAVAGE, Nathan R. DOMAGALSKI, Brendan MACK, Purushotham VEMISHETTI, Yuping QIU, Michael FENSTER, Daniel M. HALLOW, Glenn FERREIRA, Amanda ROGERS, Sha LOU, Lindsay HOBSON
  • Publication number: 20180089056
    Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.
    Type: Application
    Filed: December 11, 2017
    Publication date: March 29, 2018
    Inventors: Sooraj R. Nair, Srinivas Purushotham, Madhavan Srinivasan
  • Publication number: 20180074570
    Abstract: A method is described and in one embodiment includes, for each of a plurality of outgoing ports of a first network element: collecting data comprising a number of packets arriving the outgoing port and an amount of power consumed by the outgoing port for a first time interval; calculating a packet per watt (“P/W”) metric for the port for the first time interval, wherein the P/W metric comprises the number of packets coming into the port divided by the amount of power consumed by the port during the first time interval; repeating the collecting and calculating for a number of successive time intervals; calculating a mean P/W metric for a time period comprising the first time interval and the successive time intervals; and calculating a variance for the time period comprising the first time interval and the successive time intervals. The method further includes redirecting traffic received at the network element to the outgoing port having the lowest variance.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 15, 2018
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Anand V. Akella, Praveen Parthasarathy Iyengar, Rajendra Kumar Thirumurthi, Samar Sharma, Krishna Bharadwaj Dharwada, Vivek Purushotham
  • Patent number: 9912239
    Abstract: A power supply includes a DC-DC converter, a boost converter, an energy storage element; and a voltage clamping circuit. The DC-DC converter is connected to a power source with an output voltage in a first voltage range. The voltage clamper circuit is configured to discharge at least a portion of energy of the energy storage element and to produce current at a clamped output voltage range that is substantially equal to the first voltage range. The discharged energy provides hold-up time for the power supply.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: March 6, 2018
    Assignee: Honeywell International Inc.
    Inventors: Nishanth Beedu, Prashant Purushotham Prabhu K, Joseph Marotta, Peter Gramata, Stephen Young
  • Patent number: 9904613
    Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sooraj R. Nair, Srinivas Purushotham, Madhavan Srinivasan
  • Patent number: 9886253
    Abstract: A framework (referred to herein as Application Integration Architecture, or AIA) that formalizes and orchestrates activities in an SOA development lifecycle. In one set of embodiments, AIA can capture development-related information in a shared data store and cause the information to flow in an automated or semi-automated manner from one lifecycle phase to the next as the lifecycle progresses. This information flow can, in turn, facilitate automations at each lifecycle phase for the responsible stakeholders (e.g., solution architects, developers, installation developers, etc.), thereby enforcing SOA best practices, enhancing development productivity, and ensuring the quality of the final SOA deliverables.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: February 6, 2018
    Assignee: Oracle International Corporation
    Inventors: Annaji Garimella, Ravindran Sankaran, Nan Xie, Thirupathi Reddy Annadi, Mark James Glenn Craig, Arvind Srinivasamoorthy, Purushotham Kola
  • Publication number: 20180026536
    Abstract: A power supply includes a DC-DC converter, a boost converter, an energy storage element; and a voltage clamping circuit. The DC-DC converter is connected to a power source with an output voltage in a first voltage range. The voltage clamper circuit is configured to discharge at least a portion of energy of the energy storage element and to produce current at a clamped output voltage range that is substantially equal to the first voltage range. The discharged energy provides hold-up time for the power supply.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Nishanth Beedu, Prashant Purushotham Prabhu K, Joseph Marotta, Peter Gramata, Stephen Young
  • Publication number: 20170286251
    Abstract: Embodiments include a system for performance monitoring, the system includes a processor configured to perform a method. The method includes detecting, by a redundancy register, a change to a counter value corresponding to one of a plurality of hardware counters, wherein the redundancy register comprises a plurality of memory locations; storing, in each of the plurality of memory locations, a value indicating a change was detected for the counter value corresponding to the plurality of hardware counters, wherein each of the plurality of hardware counters map to one of the plurality of memory locations; performing read operation on a subset of the hardware counters, wherein members of the subset of the hardware counters are determined based upon the value indicating that the change was detected for the counter value corresponding to the plurality of hardware counters; and resetting the value stored in all the memory locations to a default value.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Sooraj R. Nair, Srinivas Purushotham, Madhavan Srinivasan
  • Publication number: 20170242559
    Abstract: Techniques for providing a custom app. One or more options for configuring features of an app to be generated based on an application template file that describes a generic app having a plurality of features of different types are provided via a graphical user interface. At least one application template file is modified based on one or more inputs received via the graphical user interface to select from the plurality of features to be included in the app. Code is automatically generated to provide the app having the features configured via the graphical user interface.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Stephen L. Pepper, Christopher Jolley, Purushotham Babu Naidu, Francois Lopitaux, Mandy Louise Blumreich, Kari L. Hotchkiss
  • Patent number: 9728273
    Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 8, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kanad Chakraborty, Naveen Purushotham