CONTROLLED JUNCTION TRANSISTORS AND METHODS OF FABRICATION
Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
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The present invention relates generally to semiconductor fabrication, and more particularly, to controlled junction transistors and methods of fabrication.
BACKGROUNDAs transistors disposed on integrated circuits (ICs) become smaller, transistors with source/drain extensions have become more difficult to manufacture. As critical dimensions shrink, forming source and drain extensions becomes very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because of dopant diffusion. The diffusion often extends the source and drain extension vertically into the semiconducting channel and underlying layers, while the use of alternative channel materials such as silicon-germanium or III-V materials may enhance dopant diffusivity, degrading resultant junction profiles. Highly scaled, advanced transistors benefit from precisely defined junction profiles and well-controlled gate overlap geometry to achieve well-behaved short-channel characteristics. Positioning the junction correctly with respect to the gate is challenging. Therefore, it is desirable to have improved and controllable methods of fabrication to address the aforementioned challenges.
SUMMARYEmbodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. As the final spacer material is deposited after the high temperature FEOL processes, the final spacer material may be a thermally-sensitive material which can withstand only lower processing temperatures, allowing for greater flexibility in selection of the final spacer material. That is, embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species. In this way, there is a high degree of control over the regions where dopants are placed. These controlled junctions can enable improved device performance. As an added benefit, embodiments of the present invention require no additional patterning, and can easily be integrated into an existing replacement metal gate (RMG) flow.
In a first aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a plurality of doped regions in a semiconductor channel disposed on a semiconductor substrate, wherein the plurality of doped regions are formed adjacent to a dummy gate disposed on a dummy gate oxide, the dummy gate oxide disposed on the semiconductor substrate; forming a plurality of dummy spacers, wherein the plurality of dummy spacers are disposed adjacent to the dummy gate; forming a plurality of source/drain regions adjacent to the dummy gate; depositing a dielectric layer over the source/drain regions; removing the dummy gate to form a gate cavity; removing the plurality of dummy spacers; depositing a final spacer layer; performing an etch of the final spacer layer to form final spacers; removing the dummy gate oxide; and forming a metal gate in the gate cavity.
In a second aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a metal gate on the semiconductor structure; forming a plurality of dummy spacers adjacent to the metal gate; depositing a contact metal adjacent to the plurality of dummy spacers; removing the plurality of dummy spacers to form a plurality of spacer cavities; forming doped regions in a semiconductor channel disposed at a bottom portion of each spacer cavity of the plurality of spacer cavities; and depositing a final spacer material in each spacer cavity of the plurality of spacer cavities.
In a third aspect, embodiments of the present invention provide a semiconductor structure comprising: a semiconductor substrate; two doped regions formed on a semiconductor channel disposed on the semiconductor substrate, having a gap between them; a metal gate disposed on the semiconductor substrate over the gap and extending over each of the two doped regions; a plurality of spacers formed adjacent to the metal gate and in contact with one of the two doped regions; and a cap region disposed on the metal gate.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the present teachings and together with the description, serve to explain the principles of the present teachings. Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.
Illustrative embodiments will now be described more fully herein with reference to the accompanying drawings, in which embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term “set” is intended to mean a quantity of at least one. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” “some embodiments”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments”, “in some embodiments”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. One or more features of an embodiment may be “mixed and matched” with features of another embodiment.
The terms “overlying” or “atop”, “positioned on, “positioned atop”, or “disposed on”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure (e.g., a first layer) is present on a second element, such as a second structure (e.g. a second layer) wherein intervening elements, such as an interface structure (e.g. interface layer) may be present between the first element and the second element.
While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Moreover, in particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
Claims
1.-14. (canceled)
15. A semiconductor structure comprising:
- a semiconductor substrate;
- two doped regions formed on a semiconductor channel disposed on the semiconductor substrate, having a gap between them;
- a metal gate disposed on the semiconductor substrate over the gap, and extending over each of the two doped regions;
- a plurality of spacers formed adjacent to the metal gate and in contact with one of the two doped regions; and
- a cap region disposed on the metal gate.
16. The semiconductor structure of claim 15, wherein the plurality of spacers are comprised of silicon nitride.
17. The semiconductor structure of claim 15, wherein the plurality of spacers are comprised of SiBCN.
18. The semiconductor structure of claim 15, wherein the metal gate extends over each doped region by a distance ranging from about 3 nanometers to about 10 nanometers.
19. The semiconductor structure of claim 15, wherein each spacer of the plurality of spacers has a thickness ranging from about 3 nanometers to about 10 nanometers.
20. The semiconductor structure of claim 15, wherein the metal gate includes at least one material selected from the group: tungsten, aluminum, titanium, hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide.
21. The semiconductor structure of claim 15, further comprising a dielectric layer disposed over at least the two doped regions.
22. A semiconductor structure comprising:
- a semiconductor substrate;
- a metal gate disposed on the semiconductor substrate;
- a first spacer in contact with the sides of the metal gate;
- a plurality of second spacers, each in contact with the first spacer;
- source/drain regions disposed on the semiconductor substrate, each in contact with one of the plurality of spacers;
- a plurality of doped regions disposed in the semiconductor substrate, wherein each doped region is in contact with the first spacer.
23. The semiconductor structure of claim 22, wherein the first spacer comprises silicon nitride, SiBCN, or SiOCN.
24. The semiconductor structure of claim 22, wherein the metal gate includes at least one material selected from the group: tungsten, aluminum, titanium, hafnium oxide, silicon oxide, aluminum oxide, and zirconium oxide.
25. The semiconductor structure of claim 22, further comprising a source/drain contact metal disposed over the source/drain regions.
26. The semiconductor structure of claim 25, wherein the source/drain contact metal comprises tungsten.
27. The semiconductor substrate of claim 25, further comprising a liner disposed between the source/drain contact metal and the source/drain regions.
28. The semiconductor substrate of claim 27, wherein the liner comprises titanium nitride.
29. The semiconductor substrate of claim 22, wherein the plurality of doped regions comprise arsenic, boron, antimony, or phosphorous.
Type: Application
Filed: May 13, 2016
Publication Date: Sep 1, 2016
Applicant: GLOBALFOUNDRIES INC. (Grand Cayman)
Inventors: Steven J. Bentley (Menands, NY), Ajey Poovannummoottil Jacob (Watervliet, NY), Chia-Yu Chen (Yorktown Heights, NY), Tenko Yamashita (Schenectady, NY)
Application Number: 15/154,495