Patents by Inventor Akira Mase
Akira Mase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6404476Abstract: A liquid crystal device and a manufacturing method thereof are described. The device comprises a liquid crystal panel and an auxiliary panel formed with an IC circuit for supplying driving signals to the liquid crystal device. The auxiliary substrate is separately provided with the circuit and the function thereof is tested in advance of the assembling with the liquid crystal panel. By this procedure, the yield is substantially improved.Type: GrantFiled: October 31, 1997Date of Patent: June 11, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akira Mase
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Publication number: 20020067457Abstract: A liquid crystal device and a manufacturing method thereof are described. The device comprises a liquid crystal panel and an auxiliary panel formed with an IC circuit for supplying driving signals to the liquid crystal device. The auxiliary substrate is separately provided with the circuit and the function thereof is tested in advance of the assembling with the liquid crystal panel. By this procedure, the yield is substantially improved.Type: ApplicationFiled: November 19, 2001Publication date: June 6, 2002Inventor: Akira Mase
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Patent number: 6383327Abstract: An improved method of forming an electrode pattern on a substrate is described. The substarate is coated with a first conductive film and subjected to baking. On the first conductive film is then overlied a second conductive film which mends possible fissures of the first conductive film which, besides, would produce open circuits in the pattern.Type: GrantFiled: March 30, 1994Date of Patent: May 7, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akira Mase
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Patent number: 6369788Abstract: A display and a driving method for the same capable of constructing clear visual images as described. In the display, a plurality of conductive pads are opposed to a back electrode with a light influencing medium such as a liquid crystal layer. Control signals are supplied to the conductive pads through complimentary transistors comprise a p-channel field effect transistor and an n-channel field effect transistor connected between VDD and VSS lines of a control circuit, which also supplies a bias voltage to the back electrode and gate control signals to the gate terminals of the p-channel field effect transistor and the n-channel field effect transistor. During operation, the bias voltage is inverted in order to invert the polarity of control signal applied across the light influencing medium.Type: GrantFiled: May 23, 1994Date of Patent: April 9, 2002Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Publication number: 20020033906Abstract: An electro-optical device comprising a display drive system with the display timing related to the unit time t for writing-in a picture element and to the time F for writing-in one picture is disclosed. In the device, a gradated display corresponding to the ratio of the division can be obtained by time-sharing the signal during a write-in of time t without changing the time F.Type: ApplicationFiled: September 24, 2001Publication date: March 21, 2002Inventors: Masaaki Hiroki, Akira Mase
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Publication number: 20010050664Abstract: A display and a driving method for the same capable of constructing clear visual images is described. In the display, a plurality of conductive pads are opposed to a back electrode with a light influencing medium such as a liquid crystal layer. Control signals are supplied to the conductive pads through complimentary transistors comprise a p-channel field effect transistor and an n-channel field effect transistor connected between VDD and VSS lines of a control circuit, which also supplies a bias, voltage to the back electrode and gate control signals to the gate terminals of the p-channel field effect transistor and the n-channel field effect transistor. During operation, the bias voltage is inverted in order to invert the polarity of control signal applied across the light influencing medium.Type: ApplicationFiled: August 2, 2001Publication date: December 13, 2001Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 6323528Abstract: An insulated gate field effect semiconductor device comprising a substrate having provided thereon a thin-film structured insulated gate field effect semiconductor device, said device being characterized by that it comprises a metal gate electrode and at least the side thereof is coated with an oxide of the metal. The insulated gate field effect semiconductor device according to the present invention is also characterized by that the contact holes for the extracting contacts of the source and drain regions are provided at about the same position of the end face of the anodically oxidized film established at the side of the gate. Furthermore, the present invention provides a method for forming insulated gate field effect semiconductor devices using less masks.Type: GrantFiled: July 29, 1998Date of Patent: November 27, 2001Assignee: Semiconductor Energy Laboratory Co,. Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Toshiji Hamatani
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Publication number: 20010017683Abstract: An electro-optical device comprising a display drive system with the display timing related to the unit time t for writing-in a picture element and to the time F for writing-in one picture is disclosed. In the device, a gradated display corresponding to the ratio of the division can be obtained by time-sharing the signal during a write-in of time t without changing the time F.Type: ApplicationFiled: October 3, 1997Publication date: August 30, 2001Inventors: MASAAKI HIROKI, AKIRA MASE
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Patent number: 6236064Abstract: A liquid-crystal electro-optical device capable of compensating for the operation of any malfunctioning one of TFTs (thin-film transistors) existing within the device if such a malfunction occurs. Plural complementary TFT configurations are provided per pixel electrode. Each complementary TFT configuration consists of at least one p-channel TFT and at least one n-channel TFT. The input and output terminals of the plural complementary TFT configurations are connected in series. One of the input and output terminals is connected to the pixel electrode, while the other is connected to a first signal line. All the gate electrodes of the p-channel and n-channel TFTs included in said plural complementary TFT configurations are connected to a second signal line.Type: GrantFiled: June 6, 1995Date of Patent: May 22, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akira Mase, Masaaki Hiroki
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Patent number: 6200868Abstract: A side insulation layer is formed on a side wall of a gate electrode by oxidizing (or nitrizing) a substance of the gate electrode, so that the gate electrode is insulated from the semiconductor substrate with the side insulation layer and a gate insulation film. The gap between the gate electrode and the semiconductor substrate is greater around the side wall of the gate electrode than around the center thereof. The gap between the side wall of the gate electrode and the semiconductor substrate is densely filled with an insulating substance.Type: GrantFiled: July 31, 1998Date of Patent: March 13, 2001Assignee: Toyota Jidosha Kabushiki KaishaInventors: Akira Mase, Tomoyoshi Kushida
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Patent number: 6147375Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. The thickness of the oxide is determined depending on the purpose of the oxide. In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric fields are applied to these offset regions from the gate electrode.Type: GrantFiled: September 11, 1998Date of Patent: November 14, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi
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Patent number: 6013928Abstract: An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.Type: GrantFiled: June 7, 1995Date of Patent: January 11, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi, Hideki Nemoto
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Patent number: 6004831Abstract: A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.Type: GrantFiled: May 23, 1997Date of Patent: December 21, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Akira Mase, Hideki Uochi
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Patent number: 5963278Abstract: A novel structure of an active electro-optical device is disclosed. The device is provided with complementary thin film insulated gate field effect transistors (TFTs) therein which comprise a P-TFT and an N-TFT, P-TFT and N-TFT are connected to a common signal line by the gate electrodes thereof, while the source (or drain) electrodes thereof are connected to a common signal line as well as to one of the picture element electrodes.In case of driving the active electro-optical device, a gradation display can be carried out in a driving method having a display timing determined in relation to a time F for writing one screen and a time (t) for writing in one picture element, by applying a reference signal in a cycle of the time (t), to the signal line used for a certain picture element driving selection, and by applying the select signal to the other signal line at a certain timing within the time (t), and whereby setting the value of the voltage to be applied to a liquid crystal.Type: GrantFiled: July 31, 1997Date of Patent: October 5, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 5956105Abstract: An electro-optical device including a substrate having an insulating surface and at least one thin film transistor formed on the insulating surface, wherein the thin film transistor includes a semiconductor film. An interlayer insulating film including an inorganic material is provided over the thin film transistor. A leveling film including an organic resin is formed over the substrate and covers the thin film transistor. The leveling film is prevented from directly contacting the semiconductor film by the interlayer insulating film formed over the semiconductor film. A pixel electrode is formed on the leveling film and is directly connected to the semiconductor film of the thin film transistor through an opening provided in the leveling film, wherein an edge of the organic resin film at a periphery of the opening is round.Type: GrantFiled: December 4, 1995Date of Patent: September 21, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura
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Patent number: 5946059Abstract: A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.Type: GrantFiled: November 4, 1997Date of Patent: August 31, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 5933205Abstract: A novel structure of an active electro-optical device is disclosed. The device is provided with complementary thin film insulated gate field effect transistors (TFTs) therein which comprise a P-TFT and an N-TFT. P-TFT and N-TFT are connected to a common signal line by the gate electrodes thereof, while the source (or drain) electrodes thereof are connected to a common signal line as well as to one of the picture element electrodes.In case of driving the active electro-optical device, a gradation display can be carried out in a driving method having a display timing determined in relation to a time F for writing one screen and a time (t) for writing in one picture element, by applying a reference signal in a cycle of the time (t), to the signal line used for a certain picture element driving selection, and by applying the select signal to the other signal line at a certain timing within the time (t), and whereby setting the value of the voltage to be applied to a liquid crystal.Type: GrantFiled: June 26, 1998Date of Patent: August 3, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 5905555Abstract: A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.Type: GrantFiled: December 13, 1996Date of Patent: May 18, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 5899547Abstract: nnnnA grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.Type: GrantFiled: November 4, 1997Date of Patent: May 4, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki
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Patent number: 5849611Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.Type: GrantFiled: May 31, 1995Date of Patent: December 15, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Masaaki Hiroki, Yasuhiko Takemura, Hongyong Zhang, Hideki Uochi