Patents by Inventor Akira Takashima
Akira Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9230625Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.Type: GrantFiled: March 11, 2014Date of Patent: January 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Tetsufumi Tanamoto, Akira Takashima, Yoshiaki Saito
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Patent number: 9147469Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: January 22, 2015Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Patent number: 9084311Abstract: A lighting device includes a first light source having a first S/P ratio, a second light source having a second S/P ratio that is higher than the first S/P ratio, and a controller configured to performing dimming control of light output from the first and second light sources. The controller performs the dimming control separately on the first and second light sources at least under a snow covered condition.Type: GrantFiled: July 11, 2013Date of Patent: July 14, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takashi Saito, Toshihide Mori, Ayako Tsukitani, Hiroshi Hamano, Akira Takashima, Kensuke Yamazoe, Kouichi Wada, Yoshinori Karasawa
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Publication number: 20150131363Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: January 22, 2015Publication date: May 14, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori MIYAGAWA, Shosuke FUJII, Daisuke MATSUSHITA
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Publication number: 20150126398Abstract: Dendritic cell precursor populations, dendritic cell populations derived therefrom, methods for isolating, expanding and using are disclosed.Type: ApplicationFiled: December 30, 2014Publication date: May 7, 2015Applicant: THE UNIVERSITY OF TOLEDOInventors: Akira Takashima, Hironori Matsushima, Shuo Geng
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Patent number: 8992744Abstract: A method of fabricating by co-sputtering deposition a lanthanoid aluminate film with enhanced electrical insulativity owing to suppression of deviation in composition of the film is disclosed. Firstly within a vacuum chamber, hold two separate targets, one of which is made of lanthanoid aluminate (LnAlO3) and the other of which is made of aluminum oxide (Al2O3). Then, transport and load a substrate into the vacuum chamber. Next, introduce a chosen sputtering gas into this chamber. Thereafter, perform sputtering of both the targets at a time to thereby form a lanthanoid aluminate film on the substrate surface. This film is well adaptable for use as ultra-thin high dielectric constant (high-k) gate dielectrics in highly miniaturized metal oxide semiconductor (MOS) transistors.Type: GrantFiled: July 28, 2011Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Akira Takashima
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Patent number: 8971106Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: September 8, 2014Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140376303Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira TAKASHIMA, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Publication number: 20140346434Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: ApplicationFiled: August 13, 2014Publication date: November 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hidenori MIYAGAWA, Shosuke FUJII, Akira TAKASHIMA, Daisuke MATSUSHITA
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Publication number: 20140301136Abstract: A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring line electrically connected to the semiconductor layer; a second wiring line electrically connected to the first ferromagnetic layer; and a voltage applying unit electrically connected between the first wiring line and the second wiring line to apply a first voltage between the semiconductor layer and the first ferromagnetic layer during a write operation, a magnetization direction of the first ferromagnetic layer being switchable by applying the first voltage.Type: ApplicationFiled: March 11, 2014Publication date: October 9, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki INOKUCHI, Mizue ISHIKAWA, Hideyuki SUGIYAMA, Tetsufumi TANAMOTO, Akira TAKASHIMA, Yoshiaki SAITO
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Patent number: 8854874Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array include the memory cells each including a variable resistance element in which a reset current flowing in a reset operation is smaller than a set current flowing in a set operation by not less than one order of magnitude. The control circuit performs the reset operation and the set operation for the memory cells. The control circuit performs the reset operation for all memory cells being in the low resistance state and connected to selected first interconnections and selected second interconnections.Type: GrantFiled: August 14, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Hidenori Miyagawa, Shosuke Fujii, Daisuke Matsushita
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Patent number: 8835896Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: GrantFiled: August 19, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Patent number: 8810043Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.Type: GrantFiled: August 1, 2011Date of Patent: August 19, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
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Patent number: 8779498Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first gate insulating film is arranged on the semiconductor substrate. The charge storage layer is arranged on the first gate insulating film, and includes aluminum and silicon. The second gate insulating film is arranged on the charge storage layer, and includes aluminum, silicon, and lanthanum. The control gate electrode is arranged on the second gate insulating film.Type: GrantFiled: January 25, 2013Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Daisuke Matsushita
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Patent number: 8779503Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The second insulating layer comprises a stacked structure provided in order of a first lanthanum aluminate layer, a lanthanum aluminum silicate layer and a second lanthanum aluminate layer from the charge storage layer side to the control gate electrode side.Type: GrantFiled: March 20, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Akira Takashima
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Patent number: 8772751Abstract: According to one embodiment, a memory device includes a first electrode including a crystallized SixGe1-x layer (0?x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.Type: GrantFiled: September 16, 2011Date of Patent: July 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Takashima, Daisuke Matsushita, Takashi Yamauchi, Yuuichi Kamimuta, Hidenori Miyagawa
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Patent number: 8764223Abstract: A lighting device includes first and second light emission units. The first light emission unit emits light having a relatively low color temperature and a high feeling of contrast index. The second light emission unit emits light having a relatively high S/P ratio, which is the ratio of scotopic luminance to photopic luminance. The first light emission unit illuminates a region located at a vertical upper side of a region illuminated by the second light emission unit.Type: GrantFiled: April 24, 2013Date of Patent: July 1, 2014Assignee: Panasonic CorporationInventors: Ayako Tsukitani, Takashi Saito, Akira Takashima, Kouichi Wada, Yoshinori Karasawa, Toshihide Mori, Hiroshi Hamano, Kensuke Yamazoe
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Publication number: 20140170814Abstract: A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts.Type: ApplicationFiled: February 19, 2014Publication date: June 19, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hayato OKUDA, Yasunori KAWAOKA, Akira TAKASHIMA
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Publication number: 20140167133Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Izumi HIRANO, Yuichiro Mitani, Masayasu Miyata, Yasushi Nakasaki, Koichi Kato, Daisuke Matsushita, Akira Takashima, Misako Morota
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Patent number: 8754467Abstract: A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge<Ltop and Lgate<Ltop”.Type: GrantFiled: July 18, 2013Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka