Patents by Inventor Akira Takashima

Akira Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7804128
    Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiko Ariyoshi, Akira Takashima, Shoko Kikuchi, Koichi Muraoka
  • Patent number: 7755136
    Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Akira Takashima, Tatsuo Shimizu
  • Patent number: 7736446
    Abstract: A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Takashima, Koichi Muraoka
  • Patent number: 7718490
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 18, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Watanabe, Atsuhiro Kinoshita, Akira Takashima, Daisuke Hagishima
  • Publication number: 20100078704
    Abstract: A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.
    Type: Application
    Filed: March 16, 2009
    Publication date: April 1, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsunehiro Ino, Shosuke Fujii, Jun Fujiki, Akira Takashima, Masao Shingu, Daisuke Matsushita, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20100072535
    Abstract: A nonvolatile semiconductor memory device includes a source region and a drain region provided apart from each other in a semiconductor substrate, a first insulating film provided on a channel region between the source region and the drain region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer and including a stacked structure of a lanthanum aluminum silicate film and a dielectric film made of silicon oxide or silicon oxynitride, and a control gate electrode provided on the second insulating film.
    Type: Application
    Filed: July 21, 2009
    Publication date: March 25, 2010
    Inventors: Akira Takashima, Masao Shingu, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20100065886
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.
    Type: Application
    Filed: June 10, 2009
    Publication date: March 18, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiki KAMATA, Akira TAKASHIMA
  • Publication number: 20090315659
    Abstract: A coil component having an easily discernible orientation, and a method of producing such a coil component that facilitates the injection of resin. A coil component includes a core with a winding portion, first and second flanges disposed on either end of the winding portion, and a winding accommodating region defined by the winding portion and the first and second flanges, terminal electrodes disposed on the second flange and a winding wound about the winding portion and connected to the terminal electrodes. An insulating resin is formed over the winding at the winding accommodating region. A marker made from a material the same as the insulating resin is provided at outer peripheral surface of the flanges.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Applicant: TDK CORPORATION
    Inventors: Shinichi Sato, Satoshi Kurimoto, Makoto Morita, Akira Takashima, Sumio Takahashi, Yoshiaki Kitajima
  • Publication number: 20090242963
    Abstract: In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio Si/M at a solid solubility limit of SiO2 composition in a composite oxide including metal element M and Al and set to no more than a number ratio Si/M at the condition that the dielectric constant is equal to the dielectric constant of Al2O3 and so that the number ratio Al/M is set to no less than a number ratio Al/M where the crystallization of an oxide of said metal element M is suppressed due to the Al element and set to no more than a number ratio Al/M where the crystallization of the Al2O3 is suppressed due to the metal element M.
    Type: Application
    Filed: September 19, 2008
    Publication date: October 1, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Shoko Kikuchi, Akira Takashima, Tsunehiro Ino, Koichi Muraoka
  • Publication number: 20090206393
    Abstract: A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating layer provided on the charge storage layer, and a control gate electrode provided on the block insulating layer. The charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized. The block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 20, 2009
    Inventors: Keiko Ariyoshi, Akira Takashima, Shoko Kikuchi, Koichi Muraoka
  • Publication number: 20090186474
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 23, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Watanabe, Atsuhiro Kinoshita, Akira Takashima, Daisuke Hagishima
  • Publication number: 20090114995
    Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.
    Type: Application
    Filed: August 28, 2008
    Publication date: May 7, 2009
    Inventors: Masamichi Suzuki, Masato Koyama, Yoshinori Tsuchiya, Hirotaka Nishino, Reika Ichihara, Akira Takashima
  • Publication number: 20090107586
    Abstract: A method for manufacturing a lanthanum oxide compound on a substrate includes: setting the number of H2O molecule, the number of CO molecule and the number of CO2 molecule to one-half or less, one-fifth or less and one-tenth or less per one lanthanum atom, respectively, the H2O molecule, the CO molecule and the CO2 molecule being originated from an H2O gas component, a CO gas component and a CO2 gas component in an atmosphere under manufacture; and supplying a metal raw material containing at least one selected from the group consisting of lanthanum, aluminum, titanium, zirconium and hafnium and an oxygen raw material gas simultaneously for the substrate under the condition that the number of O2 molecule are set to 20 or more per one lanthanum atom, thereby manufacturing the lanthanum oxide compound on the substrate.
    Type: Application
    Filed: March 19, 2008
    Publication date: April 30, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira TAKASHIMA, Koichi Muraoka
  • Patent number: 7518178
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film which is formed on the semiconductor substrate, a floating gate electrode which is formed on the first insulating film and made of a conductive metal oxide, a second insulating film which is formed on the floating gate electrode, has a relative dielectric constant of not less than 7.8, and is made of an insulating metal oxide of a paraelectric material, and a control gate electrode which is formed on the second insulating film and made of one of a metal and a conductive metal oxide.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: April 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Takashima, Hiroshi Watanabe, Tatsuo Shimizu, Takeshi Yamaguchi
  • Patent number: 7515028
    Abstract: A coil component having a low profile and being conducive to high-density mounting. The coil component includes a core 2 having a coil winding portion, and first and second flanges disposed on either end of the coil winding portion. The second flange is adapted to be mounted on a circuit board, and is configured of a substantially octagonal bottom surface having first and second peripheral surfaces and first through fourth omitted peripheral surfaces. The first terminal electrode is disposed across the first omitted peripheral surface and a part of the bottom surface, and the second terminal electrode is disposed across the second omitted peripheral surface and part of the bottom surface separated from the first terminal electrode. A winding is wound over the coil winding portion and has a first end electrically connected to the first terminal electrode at the first omitted peripheral surface, and a second end electrically connected to the second terminal electrode at the second omitted peripheral surface.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 7, 2009
    Assignee: TDK Corporation
    Inventors: Shinichi Sato, Satoshi Kurimoto, Makoto Morita, Akira Takashima, Sumio Takahashi, Yoshiaki Kitajima
  • Publication number: 20090057751
    Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Inventors: Keiko ARIYOSHI, Akira TAKASHIMA, Shoko KIKUCHI, Koichi MURAOKA
  • Publication number: 20090057750
    Abstract: A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer.
    Type: Application
    Filed: March 17, 2008
    Publication date: March 5, 2009
    Inventors: Akira TAKASHIMA, Shoko Kikuchi, Koichi Muraoka
  • Patent number: 7489006
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: February 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Watanabe, Atsuhiro Kinoshita, Akira Takashima, Daisuke Hagishima
  • Publication number: 20090008798
    Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.
    Type: Application
    Filed: September 15, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
  • Publication number: 20080315288
    Abstract: A memory cell of a nonvolatile semiconductor memory includes a semiconductor region, source/drain areas arranged separately from each other in the semiconductor region, a tunnel insulating film arranged on a channel region between the diffusion areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulator arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulator. The inter-electrode insulator includes lanthanoid-based metal Ln, aluminum Al, and oxygen O, and a composition ratio Ln/(Al+Ln) between the lanthanoid-based metal and the aluminum takes a value within the range of 0.33 to 0.39.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Inventors: Shoko KIKUCHI, Akira Takashima, Naoki Yasuda, Koichi Muraoka