Abstract: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.

Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.

Abstract: A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.

Abstract: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode.

Abstract: The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.

Abstract: A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.

Abstract: A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material.

Abstract: A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution; wherein the memory device further includes a means for heating the phase change material.

Abstract: The present invention in one embodiment provides a method of forming an electrode that includes the steps of providing at least one metal stud in a layer of an interlevel dielectric material; forming a pillar of a first dielectric material atop the at least one metal stud; depositing an electrically conductive material atop the layer of the interlevel dielectric material and an exterior surface of the pillar, wherein a portion of the electrically conductive material is in electrical communication with the at least one metal stud; forming a layer of a second dielectric material atop the electrically conductive material and the substrate; and planarizing the layer of the second dielectric material to expose an upper surface of the electrically conductive material.

Abstract: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.

Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: The present invention, in one embodiment, provides a memory device that includes a phase change memory cell; a first electrode; and a layer of filamentary resistor material positioned between the phase change memory cell and the first electrode, wherein at least one bistable conductive filamentary pathway is present in at least a portion of the layer of filamentary resistor material that provides electrical communication between the phase change memory cell and the first electrode.

Abstract: The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.

Abstract: A memory device utilizing a phase change material as the storage medium, the phase change material based on antimony as the solvent in a solid solution.

Abstract: Disclosed are a phase change memory cell and a method of forming the memory cell. The memory cell comprises a main body of phase change material connected directly to a bottom contact and via a narrow channel of phase change material to a top contact. The channel is tapered from the top contact towards the main body. A minimum width of the channel has a less than minimum lithographic dimension and is narrower than a width of the main body. Therefore, the channel provides a confined region for the switching current path and restricts phase changing to within the channel. In addition an embodiment of the memory cell isolates the main body of phase change material by providing a space between the phase change material and the cell walls. The space allows the phase change material to expand and contract and also limits heat dissipation.

Abstract: The present invention in one embodiment provides a method of forming a memory device including providing a first dielectric layer including at least one via containing a metal stud; providing a second dielectric layer atop the first dielectric layer; recessing the metal stud to expose a sidewall of the via; etching the sidewall of the via in the first dielectric layer with a isotropic etch step to produce an undercut region extending beneath a portion of the second dielectric layer; forming a conformal insulating layer on at least the portion of the second dielectric layer overlying the undercut region to provide a keyhole; etching the conformal insulating layer with an anisotropic etch to provide a collar that exposes the metal stud; forming a barrier metal within the collar in contact with the metal stud; and forming a phase change material in contact with the barrier metal.

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Abstract: A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.