Abstract: For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Abstract: A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.

Abstract: For one disclosed embodiment, a plurality of processor cores of a multicore processor may be operated at variable performance levels. One processor core may operate at a performance level different than a performance level at which another processor core may operate. Performance levels of multiple processor cores may be identified. Power consumption of the plurality of processor cores may be controlled based at least in part on the identified performance levels. Other embodiments are also disclosed.

Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.

Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Abstract: A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.

Abstract: Methods and mechanisms to simultaneously regulate two or more supply voltages provided to an integrated circuit by a voltage regulator. In an embodiment of the invention, a voltage regulation message exchanged between the integrated circuit and the voltage regulator includes an identifier indicating two or more supply voltages selected from a plurality of supply voltages provided to the integrated circuit by the voltage regulator, where the voltage regulation message relates to the indicated two or more supply voltages. In another embodiment, the voltage regulation message indicates a desired supply voltage level to which the indicated two or more supply voltages are to transition.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.