Patents by Inventor An-Cheng Chang

An-Cheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868013
    Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Tsai, Ming-Chi Huang, Zoe Chen, Wei-Chin Lee, Cheng-Lung Hung, Da-Yuan Lee, Weng Chang, Ching-Hwanq Su
  • Patent number: 10867836
    Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Sung Chang, Ching-Ray Chen, Yen-Cheng Liu, Shang-Ying Tsai
  • Patent number: 10867862
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Patent number: 10865884
    Abstract: A cylinder valve assembly includes an actual on-off control subsystem. An intermediate chamber extends between a probe chamber and proximal chamber of the valve body along a main axis. A control port extends radially of the main axis. A valve pin is received by the intermediate chamber and movable between closed and open positions. A control plug is received by the control port and actuatable between on and off positions. Fluid communication between the proximal and probe chambers through the valve body is enabled when the valve pin is in the open position and the control plug is in the on position. Contrastingly, such fluid communication is prevented if either the valve pin is in the closed position or the control plug is in the off position. The control plug is preferably located in radial alignment along the main axis with at least a portion of the valve pin.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: YSN Imports, Inc.
    Inventors: Shmuel Dovid Newman, Chin-Cheng Chang
  • Publication number: 20200388706
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Ching-Wei TSAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kuo-Cheng CHIANG, Ru-Gun LIU, Wei-Hao WU, Yi-Hsiung LIN, Chia-Hao CHANG, Lei-Chun CHOU
  • Publication number: 20200387247
    Abstract: A touch system includes a processor and a touch array. The touch array includes touch units. Each of the touch units includes a driving electrode, a first sensing electrode, and a second sensing electrode. A first capacitor is formed between the first sensing electrode and the driving electrode. A second capacitor is formed between the second sensing electrode and the driving electrode. The processor is configured to: determine whether the touch array operates in an underwater mode according to the first original capacitance value and the second original capacitance value; determine whether a conductor touch event occurs according to a first threshold value and a voltage across the first capacitor when the touch array operates in the underwater mode; and determine whether a non-conductor touch event occurs according to a second threshold value and a voltage across the second capacitor when the touch array operates in the underwater mode.
    Type: Application
    Filed: July 17, 2019
    Publication date: December 10, 2020
    Inventors: Hsien-Ying CHOU, Chun-Ta CHEN, Chih-Lin LIAO, Fu-Cheng WEI, Fu-Chiang CHUANG, Pi-Tsang CHANG
  • Publication number: 20200388616
    Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chung-Chiang Wu, Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Publication number: 20200383803
    Abstract: A registration system including a bone pin guide and a bone pin clamp. The bone pin guide may include a guide body, a first guide including a first guide through-hole having a first longitudinal axis, and a second guide including a second guide through-hole having a second longitudinal axis. The bone pin guide may guide first and second bone pins into a bone via the first and second guides. The bone pin clamp may include a clamp body, first, second, and third clamp through-holes extending through the clamp body, a plurality of registration indents defined on the clamp body, and a clamping mechanism including at least one adjustable fastener. The bone pin clamp may receive the first and second bone pins in the first and third clamp through-holes and guide a third bone pin into the bone via the second clamp through-hole.
    Type: Application
    Filed: February 26, 2019
    Publication date: December 10, 2020
    Applicant: MAKO Surgical Corp.
    Inventors: Zhu Wu, Sunil Gupta, Ta-Cheng Chang, Zenan Zhang, Kevin Bechtold, Matt Thompson, Eric Branch, Varun Chandra, Ahmet Bagci
  • Publication number: 20200386390
    Abstract: A slim linear LED lighting device is provided, including: a printed circuit board on which a connecting circuit is provided, at least one power input component, and a plurality of LED Bars. The LED Bar is formed by a plurality of the same kind of LED chips, and has a slim strip-shaped condensing lens structure integrally formed in the LED Bar packaging process by molding process to control the beam angle of the LED Bar and therefore the light distribution of the slim linear LED lighting device. The LED Bar's condensing lens has a small cross-sectional dimension; therefore the effective utilization factor of the light is improved as the slim linear LED lighting device is applied to a linear automotive lamp designed with a thin light blade structure.
    Type: Application
    Filed: October 30, 2019
    Publication date: December 10, 2020
    Inventors: YEN-CHENG CHEN, SHENG-HUA YANG, HSUAN-JUNG TSAI, CHENG-TAI JAO, CHIH-CHIANG CHANG
  • Patent number: 10861954
    Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Yi-Ren Chen, Chang-Yin Chen, Yi-Jen Chen, Ming Zhu, Yung-Jung Chang, Harry-Hak-Lay Chuang
  • Patent number: 10860758
    Abstract: A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: December 8, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chien-Cheng Liu, Shih-Chih Liu, Yun-Chih Chang, Shu-Yi Kao
  • Patent number: 10861977
    Abstract: A device includes a semiconductive substrate, a stop layer over the semiconductive substrate, first and second semiconductive fins over the stop layer, a fin isolation structure between the first and second semiconductive fins, and a spacer at least partially extending along a sidewall of the fin isolation structure. A bottom of the fin isolation structure is lower than a top of the stop layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10860150
    Abstract: A touch system includes a processor and a touch array. The touch array includes touch units. Each of the touch units includes a driving electrode, a first sensing electrode, and a second sensing electrode. A first capacitor is formed between the first sensing electrode and the driving electrode. A second capacitor is formed between the second sensing electrode and the driving electrode. The processor is configured to: determine whether the touch array operates in an underwater mode according to the first original capacitance value and the second original capacitance value; determine whether a conductor touch event occurs according to a first threshold value and a voltage across the first capacitor when the touch array operates in the underwater mode; and determine whether a non-conductor touch event occurs according to a second threshold value and a voltage across the second capacitor when the touch array operates in the underwater mode.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 8, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Hsien-Ying Chou, Chun-Ta Chen, Chih-Lin Liao, Fu-Cheng Wei, Fu-Chiang Chuang, Pi-Tsang Chang
  • Publication number: 20200381980
    Abstract: The present invention provides a cooling mechanism between a linear motor rotor and a platform coupled thereto, characterized essentially in that a cooling portion is provided between the rotor and the platform, and further in that heat transfer is blocked between the cooling portion and the platform, thereby preventing heat received by the cooling portion during heat dissipation from being transferred to the platform, so as to ensure the precision of the platform.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Min-Chang HUANG, Cheng-Te CHI, Chao-Chin TENG
  • Publication number: 20200381257
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. A top surface of the dielectric fin is close to the epitaxial structure. The semiconductor device structure includes a silicide layer wrapping around the epitaxial structure and partially between the dielectric fin and the epitaxial structure. The silicide layer covers a lower surface of the epitaxial structure, and the lower surface is lower than the top surface of the dielectric fin.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung LIN, Jung-Hung CHANG, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20200377717
    Abstract: A polymer composition includes a polyester, a multifunctional compound, and a polymeric compound containing a salt of a metal. The multifunctional compound is one of polyacid, polyanhydride, and the combination thereof. Based on the polymer composition, the metal is present in an amount ranging from 0.01 mol % to 5.0 mol %. Also disclosed herein are an article prepared from the polymer composition and a method for preparing a resin composition from the polymer composition.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 3, 2020
    Inventors: Yu-Cheng LIAO, Mao-Yuan CHIU, Li-Ling CHANG
  • Publication number: 20200381532
    Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Publication number: 20200381425
    Abstract: A monolithic integration of enhancement mode (E-mode) and depletion mode (D-mode) field effect transistors (FETs) comprises a compound semiconductor substrate overlaid by an epitaxial structure overlaid by source and drain electrodes. The epitaxial structure includes from bottom to top sequentially a buffer layer, a channel layer, a Schottky barrier layer, a first etch stop layer, and a first cap layer. The respective first gate metal layers of the D-mode and E-mode FET are in contact with the first etch stop layer. The D-mode and E-mode gate-sinking regions are beneath the respective first gate metal layers of the D-mode and E-mode gate electrode at least within the first etch stop layer. The first gate metal layer material of the D-mode is the same as that of the E-mode, where the first gate metal layer thickness of the E-mode is greater than that of the D-mode.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Chia-Ming CHANG, Jung-Tao CHUNG, Yan-Cheng LIN, Lung-Yi TSENG
  • Publication number: 20200381545
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
    Type: Application
    Filed: December 5, 2019
    Publication date: December 3, 2020
    Inventors: Kuo-Cheng Chiang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang, Jung-Hung Chang
  • Patent number: 10854505
    Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng