Abstract: In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a switching mechanism coupled to a wireless power transmitting device, wherein the switching mechanism is configured to selectively control operation of a transmitting coil in the wireless power transmitting device.

Abstract: This document discloses one or more systems, apparatuses, methods, etc. for integrating coil antennas in a carbon fiber chassis portable device. More particularly, the carbon fiber chassis portable device containing unidirectional weave carbon fibers in its chassis—to support near field communications (NFC) related functions—is described.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

Abstract: A method, non-transitory computer readable medium, and apparatus that establishes a connection with a host computing device. One or more processes running on the host computing device are identified. One or more hooking operations performed in the one or more identified processes are identified. One or more suspected key logging actions are identified from the one or more identified hooking operations based on one or more of a first set of rules and output.

Abstract: A caching system and methodology for data in a memory for faster access to commonly-used data by other applications and computer devices on a network. The memory can include a solid-state drive (SSD) array for the cache memory that has read-bias, in addition to a magnetic hard drive array. The system uses a logical set of slots to hold identifiers for specific groups of data that can be placed into cache memory and each identifier has a usage attribute that changes based upon the usage of the specific group of data and causes the identifier to move within the set of slots and potentially into cache memory.

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.

Abstract: Described herein are techniques related one or more systems, apparatuses, methods, etc. for reducing induced currents in a apparatus chassis. For example, a fractal slot is constructed in the apparatus chassis to reduce the induced currents, and enhance passage of magnetic fields through the apparatus chassis. In this example, the fractal slot may include a no-self loop fractal space filling curve shape to provide high impedance to the induced currents.

Abstract: A circuit including headset type detection provides compatibility with different transducer types, such as headphones provided by different manufacturers. An audio circuit that generates or receives an audio signal includes electrical terminals for coupling to a transducer device, at least one of which carries the audio signal. A transducer device type detection circuit is included and detects a type of a transducer device coupled to the audio device from characteristics measured at the multiple electrical terminals when the transducer is coupled to the audio device. The circuit also includes a configuration control circuit for altering a configuration of the audio device according to a detected type of the transducer device.

Abstract: Apparatus, methods, computer program products, and software for reducing interference occurring when a capacity booster cell has a coverage area within the overlapping coverage areas of more than one coverage cell are disclosed. Essentially, weights are assigned, either by individual capacity booster cells or by zone controllers with which a plurality of capacity booster cells communicate, to coverage cells. The interfering coverage cells are ranked in accordance with the assigned weights, and the metrics to be reported to each of the interfering coverage cells are adjusted in view of the assigned weights. The adjusted metrics are then reported to each of the interfering coverage cells to influence the ABS muting pattern subsequently used by each of said interfering coverage cells.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Described herein are techniques related to near field coupling and proximity sensing operations. For example, a proximity sensor uses a coil antenna that is utilized for near field communications (NFC) functions. The proximity sensor may be integrated into an NFC module to form a single module.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

Abstract: Systems and methods for providing anti-malware protection on storage devices are described. In one embodiment, a storage device includes a controller, firmware, and memory. The firmware communicates with an authorized entity (e.g., external entity, operating system) to establish a secure communication channel. The system includes secure storage to securely store data.

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Abstract: In vivo positionable filtration devices are provided that filter one or more therapeutic agents in blood flowing in a blood vessel. The filtration devices include an elongated member and a filtering component coupled to the elongated member. The elongated member and the filtering component are dimensioned for positioning within a blood vessel of a human or non-human animal. Further, the filtering component includes a filtration material to filter the one or more therapeutic agents from blood. Methods of in vivo filtration of one or more therapeutic agents are also provided. The methods include positioning a filtration device in a blood vessel of a body of a human or non-human animal, and administering a therapeutic agent upstream from the target tissue site to direct flow of the therapeutic agent to the target tissue site and then to the filtration device. The filtration device is positioned downstream from a target tissue site.

Abstract: Systems and techniques for handover management in wireless communication networks. An apparatus, such as a base station, receives information relating to load conditions and computes handover threshold information based on the information relating to the load conditions. The information relating to the load conditions may comprise information received from other base stations, and the base station may in turn share its own information. Information may be shared through direct communication between base stations, or may be managed by a controller. Handover thresholds may be set for user devices based on the load metric information.

Abstract: Described herein are techniques related to near field communication and wireless power transfers. A portable device may include a modular antenna that offers consistent characteristics independent of integration environment. The modular antenna may include a continuous loop of coil antenna and a ferrite material that are encapsulated by a shield. The shield may form a “U” shape configuration to encapsulate the top layer coil antenna and the middle layer ferrite material in all three sides, which are defined by a bottom portion, an outer wall, and an inner wall. Furthermore, the shield may include an outer rim and an inner rim to maintain the same coil antenna characteristics in the modular antenna.

Abstract: An antenna assembly comprises a computer expansion card comprising a metallic layer which forms a radiating element or a metallic shield which forms the radiating element and a feed line coupled to the radiating element. Other embodiments may be described.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.