Patents by Inventor Anand S

Anand S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9012284
    Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
  • Publication number: 20150093988
    Abstract: A mechanism is described for facilitating hybrid communication between devices according to one embodiment. A method of embodiments, as described herein, includes coupling an inductive coil of a near proximity circuitry with a capacitive pad of a body area circuitry to form a hybrid circuitry, and facilitating, via the hybrid circuitry, the hybrid communication between a plurality of devices.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Kwan Ho Lee, Akihiro Takagi
  • Patent number: 8994104
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 8983388
    Abstract: A first base station communicates (102) with a second base station (wherein an ongoing communication cannot be handed over from the first base station to the second base station and wherein the first and second base station each employ, at least in part, a same set of carrier resources) to prevent interference by usage of the second base station with a user of the first base station. By one approach, this activity can be based, at least in part, upon receipt (101) of a message from an end user platform indicating that a carrier resource that is presently being used by the end user platform is being interfered with by the second base station. By another approach, this activity can take place prior to any actual such interference.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: March 17, 2015
    Assignee: Google Technology Holdings LLC
    Inventors: Guang Han, Rajeev Agrawal, Anand S. Bedekar
  • Publication number: 20150069473
    Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Michael L. Hattendorf, Subhash M. Joshi
  • Publication number: 20150060945
    Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu
  • Publication number: 20150054031
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 26, 2015
    Applicant: Intel Corporation
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, MICHAEL J. JACKSON, HAROLD W. KENNEL
  • Patent number: 8966160
    Abstract: In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam, Richard P. Mangold
  • Patent number: 8957476
    Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
  • Publication number: 20150044963
    Abstract: Described herein are techniques related to near field coupling and WLAN dual-band operations. For example, a WLAN dual-band utilizes the same coil antenna that is utilized for near field communications (NFC) functions. The WLAN dual-band may be integrated into an NFC module to form a single module.
    Type: Application
    Filed: March 30, 2012
    Publication date: February 12, 2015
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Patent number: 8937865
    Abstract: In general, techniques are described for scheduling traffic for delivery over an aggregated bundle of links. A network device comprising an interface and a data plane may implement the techniques. The interface receives packets associated with packet flows. The data plane associates each of the packet flows with a different link of an aggregated bundle of links. The data plane monitors transmission of the packets via the links to determine a representation of an amount of data sent per link. The data plane further determines that bandwidth utilization does not conform to a desired bandwidth utilization based on the determined representation of the amount of data sent per link. The data plane then re-associates the packet flows to different links of the aggregated bundle based on the determination that the bandwidth utilization does not conform to the desired bandwidth utilization.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: January 20, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Nitin Kumar, Alex Baban, Surya Nimmagadda, Alok Khambatkone, Saravanan Masilamani, Anand S. Athreya, Vipul Deokar
  • Publication number: 20150008484
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Application
    Filed: September 24, 2014
    Publication date: January 8, 2015
    Applicant: INTEL CORPORATION
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Patent number: 8929280
    Abstract: A method for prioritizing Mobile IP between PMIP and CMIP includes the steps of connecting a mobile device (118) to a communication network (102) and determining (308) if the network provides mobility control, such as the network being PMIP-enabled. When it is determined that the network provide mobility control, the mobility function is assigned (312) to the network and is therefore given priority over the mobility function provided by the mobile device. It can be determined (304) that the mobile station also includes a mobility control so that when the network is not PMIP-enabled the mobile station controls (314) layer 3 mobility and the Mobile IP function.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: January 6, 2015
    Assignee: Motorola Mobility LLC
    Inventors: Anand S. Bedekar, Rajeev Agrawal, Suresh Kalyanasundaram
  • Patent number: 8907859
    Abstract: Described herein are techniques related to near field coupling and wireless power transfers. A mobile device may include an edge-emitting antenna that offers ultra slim, all-metallic chassis packaging option with no cutout, uses lesser area, has robust mechanical strength, and provides EMI/ESD protection. In one example, an inductor coil is wrapped around a magnetic core and a pair of conductive layers is configured to interpose the magnetic core and the inductor coil between them to expose an edge of the magnetic core. The inductor coil being operable in a transmit mode to generate a magnetic field in response to a current passing through it. The edge is configured to enhance outward radiation of the magnetic field. Based on simulation results, the edge-emitting antenna occupies less space and provides an acceptable level of performance for coupling coefficients compared to conventional antenna.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Hao-Han Hsu, Dong-Ho Han, Songnan Yang, Anand S Konanur, Chung-Hao Joseph Chen
  • Patent number: 8901537
    Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu
  • Publication number: 20140346886
    Abstract: Described herein are techniques related to near field coupling and wireless power transfers. A portable device may include a coil antenna that includes an upper loop and a lower loop to form a figure-eight arrangement. The figure-eight coil antenna arrangement is wrapped against top and bottom surfaces of a component to establish near field coupling through front side, top side, bottom side, or corner side of the portable device. Further, a flux guide may be placed between the coil antenna and the component to facilitate magnetic flux at the upper loop and the lower loop to induce current of the same phase during receive mode. During transmit mode, the flux guide facilitates the magnetic flux at the upper loop and the lower loop to generate magnetic fields of the same direction.
    Type: Application
    Filed: February 13, 2012
    Publication date: November 27, 2014
    Inventors: Songnan Yang, Anand S. Konanur, Bin Xiao, Ulun Karacaoglu
  • Patent number: 8896066
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Harold W. Kennel
  • Publication number: 20140302808
    Abstract: According to one embodiment disclosed herein, there is provided an antenna module including a self-identification mechanism that may be used by one or more wireless circuits for management purposes. The self-identification mechanism may, for example, take the form of an integrated circuit (IC) device or chip that stores a serial number that may function as a unique identifier for an antenna on which it is mounted or associated. In one embodiment, a wireless module, for example containing RF components for sending and receiving signals from the antenna, queries the serial number device, and acquires the serial number for the antenna. The wireless module can use the serial number for any number of purposes, and in particular to verify that the antenna connected is a compliant antenna that will operate within the range, within the limits, and/or with the performance specified for the radio circuits within the wireless module.
    Type: Application
    Filed: December 29, 2011
    Publication date: October 9, 2014
    Inventors: Ulun Karacaoglu, Robert Paxman, Anand S. Konanur
  • Patent number: 8847281
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Publication number: 20140239345
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 28, 2014
    Applicant: INTEL CORPORATION
    Inventors: Boyan BOYANOV, Anand S. MURTHY, Brian S. DOYLE, Robert S. CHAU