Abstract: Changes in the distribution of memory cells across memory states allow calculation of Bit Error Rate (BER). Comparison of test data stored in memory and a known good copy of the test data provides test data BER from which user data BER may be obtained. Data may be handled differently according to its BER.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.

Abstract: A system and method of programming user data into a memory cell includes receiving a first user data to be programmed in a memory controller, selecting a memory cell for programming the first user data and measuring at least one health characteristic of the selected memory cell. At least one programming parameter of the selected memory cell is adjusted and the first user data is programmed to the selected memory cell using the adjusted programming parameter corresponding to the selected memory cell.

Abstract: A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path.

Abstract: A method includes, in a data storage device including a resistive memory, receiving an erase command to erase a portion of the resistive memory. The method further includes sending shaped data to be stored at the portion of the resistive memory responsive to the erase command.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A data storage device includes a memory die. The memory die includes a resistive memory. A method includes determining a power characteristic associated with performing a write process to write data to the resistive memory. The method further includes initiating a modified write process in response to detecting that the power characteristic satisfies a threshold.

Abstract: A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory.

Abstract: A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: A data storage device includes a memory and a controller. A method includes accessing data stored at the memory to generate a first logical page. The method further includes generating a second logical page. Generating the second logical page includes accessing parity information from the memory. The parity information is associated with the first logical page. The method further includes generating a third logical page. Generating the third logical page includes modifying a first value of the first logical page based on a second bit value of the second logical page.

Abstract: Changes in the distribution of memory cells across memory states allow calculation of Bit Error Rate (BER). Comparison of test data stored in memory and a known good copy of the test data provides test data BER from which user data BER may be obtained. Data may be handled differently according to its BER.

Abstract: A data storage device includes a memory and a controller. A method includes accessing data stored at the memory to generate a first logical page. The method further includes generating a second logical page. Generating the second logical page includes accessing parity information from the memory. The parity information is associated with the first logical page. The method further includes generating a third logical page. Generating the third logical page includes modifying a first value of the first logical page based on a second bit value of the second logical page.

Abstract: A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed.

Abstract: Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data.

Abstract: A method performed at a data storage device includes adjusting a first read voltage and a second read voltage to form sets of read voltages. First representations of data are read from a logical page in the non-volatile memory according to the sets of read voltages. The first representations of the data correspond to multiple values of the first read voltage and the second read voltage. The first representations of the data are stored in a memory and second representations of the data are generated based on the first representations. A value of the first read voltage is selected based on syndrome weights corresponding to the second representations.

Abstract: Head mountable camera devices, systems, and methods are disclosed.

Abstract: Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data.

Abstract: Holders for portable memory cards and methods for manufacturing such holders are provided. A holder for a portable memory card described herein is configured to attach to a host device such that a portable memory card can travel with a host even when the portable memory card is not being used with the host. A holder for a portable memory card described herein may have a low profile design compatible with host electronic devices of increasingly small form factor, such as mobile phones and portable media players. A holder for a portable memory card may also include a lock for locking a portable memory card in a compartment formed by the memory card holder to prevent accidental removal of the portable memory card from the compartment.