Patents by Inventor Benjamin Chu

Benjamin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10112150
    Abstract: Membranes of the present disclosure possess very thin barrier layers, with high selectivity, high throughput, low fouling, and are long lasting. The membranes include graphene and/or graphene oxide barrier layers on a nanofibrous supporting scaffold. Methods for forming these membranes, as well as uses thereof, are also provided. In embodiments, an article of the present disclosure includes a nanofibrous scaffold; at least a first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof on at least a portion of a surface of the nanofibrous scaffold; an additive such as crosslinking agents and/or particles on an outer surface of the at least first layer of nanoporous graphene, nanoporous graphene oxide, or combinations thereof.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 30, 2018
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin Chu, Benjamin S. Hsiao, Hongyang Ma, Zhe Wang
  • Publication number: 20180301563
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 18, 2018
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10096683
    Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Sanaz Gardner, Seung Hoon Sung, Robert S. Chau
  • Patent number: 10096682
    Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Seung Hoon Sung, Marko Radosavljevic, Benjamin Chu-Kung, Sherry Taft, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10096474
    Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz, Sansaptak Dasgupta, Seung Hoon Sung, James M. Powers, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Robert S. Chau
  • Patent number: 10096709
    Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
  • Publication number: 20180261669
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Application
    Filed: February 8, 2018
    Publication date: September 13, 2018
    Inventors: Van H. LE, Benjamin CHU-KUNG, Harold Hal W. KENNEL, Willy RACHMADY, Ravi PILLARISETTY, Jack T. KAVALIEROS
  • Patent number: 10074718
    Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20180219087
    Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.
    Type: Application
    Filed: September 25, 2014
    Publication date: August 2, 2018
    Inventors: Sansaptak DASGUPTA, Han Wui THEN, Sanaz K. GARDNER, Marko RADOSAVLJEVIC, Seung Hoon SUNG, Benjamin CHU-KUNG, Robert S. CHAU
  • Patent number: 10032911
    Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert S. Chau, Sansaptak Dasgupta, Marko Radosavljevic, Benjamin Chu-Kung, Seung Hoon Sung, Sanaz Gardner, Ravi Pillarisetty
  • Patent number: 10026845
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10020371
    Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Willy Rachmady, Van H. Le, Gilbert Dewey, Niloy Mukherjee, Matthew V. Metz, Han Wui Then, Marko Radosavljevic
  • Publication number: 20180158933
    Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.
    Type: Application
    Filed: June 27, 2015
    Publication date: June 7, 2018
    Inventors: Van H. LE, Gilbert DEWEY, Benjamin CHU-KUNG, Ashish AGRAWAL, Matthew V. METZ, Willy RACHMADY, Marc C. FRENCH, Jack T. KAVALIEROS, Rafael RIOS, Seiyon KIM, Seung Hoon SUNG, Sanaz K. GARDNER, James M. POWERS, Sherry R. TAFT
  • Publication number: 20180158841
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, DANIEL B. AUBERTINE, TAHIR GHANI, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, CHANDRA S. MOHAPATRA, KARTHIK JAMBUNATHAN, GILBERT DEWEY, WILLY RACHMADY
  • Publication number: 20180151684
    Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.
    Type: Application
    Filed: June 27, 2015
    Publication date: May 31, 2018
    Inventors: Benjamin CHU-KUNG, Van H. LE, Rafael RIOS, Gilbert DEWEY, Scott B. CLENDENNING, Jack T. KAVALIEROS
  • Patent number: 9972686
    Abstract: Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a channel region that comprises a germanium tin portion of a fin such that the fin includes a buffer layer disposed over a substrate and the germanium tin portion disposed over the buffer layer.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Willy Rachmady, Roza Kotlyar, Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Gilbert Dewey, Benjamin Chu-Kung, Jack T. Kavalieros
  • Patent number: 9968892
    Abstract: A high flux and low pressure drop microfiltration (MF) membrane and a method for making the MF membrane. The microfiltration membranes are formed by a method that includes: preparing a nanofibrous structure; and modifying the surface of the nanofibrous structure with a surface modifier. The nanofibrous structure includes an electrospun nanofibrous scaffold or a polysaccharide nanofiber infused nanoscaffold or mixtures thereof. The electrospun nanofibrous scaffold can include polyacrylonitrile (PAN) or polyethersulfone (PES))/polyethylene terephthalate (PET) or mixtures thereof. The surface modifier includes polyethylenimine (PEI) and polyvinyl amine (Lupamin) cross-linked by ethylene glycol diglycidyl ether (EGdGE)/glycidyltrimethylammonium chloride (GTMACl) or poly(1-(1-vinylimidazolium)ethyl-3-vinylimdazolium dibromide (VEVIMIBr).
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: May 15, 2018
    Assignee: NATIONAL SCIENCE FOUNDATION
    Inventors: Benjamin Chu, Benjamin S. Hsiao, HongYang Ma
  • Patent number: 9947780
    Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 9931611
    Abstract: Articles are provided for absorbing fluids. In embodiments, the articles of the present disclosure are modified to make them hydrophobic, thereby decreasing their affinity for water and similar liquids, while increasing their affinity for other hydrophobic materials, including oil. After use, the articles, in embodiments polyurethane sponges, may have their absorbed materials removed therefrom, and the articles may then be reused to absorb additional materials.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 3, 2018
    Assignee: The Research Foundation for the State University of New York
    Inventors: Benjamin Chu, Benjamin Hsiao, Zhe Wang
  • Publication number: 20180086851
    Abstract: The present disclosure provides methods for producing carboxylated nanocelluloses. Compared with conventional methods, the methods of the present disclosure are simple and cost-effective in the production of carboxylated (or carboxy) nanocelluloses, in embodiments nanofibers and/or nanowhiskers, directly from raw biomass, including lignocellulose wood, non-wood sources, non-lignocellulose wood, lignocellulose or pure cellulose. The carboxy groups on the surface of nanocellulose thus produced can then be easily modified into functional derivatives such as amide, acetate, ether, ester, etc. The resulting nanocelluloses may be used to form purifying agents and/or filters to remove impurities from wastewater.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Benjamin S. Hsiao, Benjamin Chu, Priyanka R. Sharma