Abstract: A storage device includes: a nonvolatile memory including a plurality of memory regions; and a controller configured to transmit to the host, when a normal read command and a logical address are received from a host, an upload request for uploading map data related to a first memory region corresponding to the logical address among the plurality of memory regions based on a map caching count related to the first memory region.

Abstract: A memory system, a memory controller and an operating method of the memory controller. The memory controller may include a host interface configured to communicate with a host; a memory interface configured to communicate with a memory device; and a control circuit configured to control an operation of the memory device. The control circuit may selectively determine to use a cache for an operation indicated by a command received from the host, depending on a number of memory dies, of a plurality of memory dies in the memory device, detected to be in an activated state.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and an external electrode. A cover portion of the body has curved corners, and a radius of curvature, R, of each of the curved corners and a thickness, T, of the body satisfy a condition of 10 ?m?R?T/3, and a width, W, and a thickness, T, of the body satisfy a condition of T/W<0.8.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory controller having a map manager and preload mapping information storage, and a memory device having logical-to-physical mapping information. The memory controller determines and obtains from the memory device, preloads mapping information, and then stores the preload mapping information in the preload mapping information storage, before a map update operation of the logical-to-physical mapping information is performed. The preload mapping information includes logical-to-physical mapping information to be updated.

Abstract: A multilayer capacitor includes a body including a stacked structure of a plurality of dielectric layers and a plurality of internal electrodes, wherein, in the body, corners of cover portions are formed as curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and 0.8?Tg/Wg?1.2 in which Wg is a margin of the body in a width direction, and Tg is a margin of the body in a thickness direction.

Abstract: The memory controller is provided to include: an operation controller configured to control memory devices to read first to third source pages and a source parity page in a source stripe and perform program operations on first to third target pages and a target parity page in a target stripe, a program data determiner configured to determine first to third program data to be programmed in the first to third target pages and to determine data read successfully from the first and second source pages as the first and second program data and determine recovery data as the third program data upon whether the read operation for the third source page has failed, and a parity calculator configured to generate calculation data by using the first and second program data, and generate the recovery data by using source parity data and the calculation data.

Abstract: A controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.

Abstract: A memory system includes a memory device for storing first and second mapping information associated with target logical addresses for an unmap command, and a controller for loading the first and second mapping information from the memory device, comparing a size of target map data corresponding to the target logical addresses with a threshold value, sorting a plurality of map segments mapped with a plurality of target logical groups including the target logical addresses, respectively, into a plurality of regions based on a result of the comparing, and performing an unmap operation on each of the map segments included in the regions, wherein the first mapping information includes information on mapping relationships between the plurality of map segments and the plurality of target logical groups, and the second mapping information includes information on mapping relationships between the target logical addresses and corresponding physical addresses.

Abstract: A data storage device may include: a nonvolatile memory device; and a controller configured to control an operation of the nonvolatile memory device. In response to an unmap command is received from a host, the controller may generate an unmap descriptor including logical block addresses to be trimmed, stores the generated unmap descriptor, and transfer a response signal to the host. The response signal indicates that an unmap caching operation corresponding to the unmap command is completed.

Abstract: The memory controller includes an unmap controller configured to receive unmap information from a host, calculate operation times required to perform a plurality of respective unmap operations based on the unmap information, and output an unmap command for an unmap operation having a relatively short operation time among the plurality of unmap operations as a result of the calculation; a buffer memory configured to store a plurality of types of address mapping information; and a control processor configured to control the unmap controller and the buffer memory in response to a command received from the host.

Abstract: A multilayer capacitor includes a body and external electrodes on external surfaces of the body. The body includes a plurality of internal electrodes alternately laminated with dielectric layers. The external electrodes are electrically connected to the internal electrodes. Edges of cover portions of the body are rounded. The rounded edges have a radius of curvature R and the body has a thickness T, such that R and T satisfy 10 ?m?R?T/4. Among the plurality of internal electrodes, an internal electrode in each of the cover portions has a width less than that of an internal electrode of the central portion.

Abstract: Methods, systems and devices for efficiently performing a read fail recovery operation are described. An exemplary data storage device includes a nonvolatile memory device including a page group in which program-completed pages and program-in-progress pages are mixed, a buffer memory configured to buffer data and an XOR parity to be stored in pages of the page group. The data storage device also includes a recovery circuit configured to recover an error of read-failed data, and a processor configured to control the recovery circuit to read data and an XOR parity corresponding to the program-in-progress pages from the buffer memory. The processor is also configured to recover the error of the read-failed data using data corresponding to remaining program-completed pages other than a page in which the read-failed data is stored among the program-completed pages, and the data and the XOR parity read from the buffer memory.

Abstract: A multilayer capacitor includes a body including a stacked structure having dielectric layers, and internal electrodes, and external electrodes. The body has a central portion, and cover portions disposed above and below the central portion, the body has a first surface and a second surface to which the internal electrodes are exposed and which oppose each other, a third surface and a fourth surface which oppose each other in the stacking direction of the dielectric layers, and a fifth surface and a sixth surface which are connected to the first to fourth surfaces and oppose each other, and a surface roughness of each of the third to sixth surfaces of the body is greater than a surface roughness of each of the first and second surfaces of the body.

Abstract: A data storage device includes a memory array including a plurality of memory cells; and a controller in communication with the memory array and configured to: store, in a map update buffer, one or more map segments including one or more logical address to be unmapped; determine, among logical address to physical address (L2P) entries of the one or more map segments stored in the map update buffer, L2P entries having the same memory block number; and selectively perform a first unmap operation or a second unmap operation according to whether all the L2P entries stored in the map update buffer have the same memory block number.

Abstract: A controller may include a memory configured to store a map update list in which information of map segments whose mapping information is to be updated is registered The controller may also include an unmap module. The unmap module may, in response to receiving an unmap command, generate a list information bitmap indicating map segments which are already registered in the map update list, check, using the generate list information bitmap, whether one or more unmap target map segments corresponding to the unmap command overlap the map segments registered in the map update list, using the generate list information bitmap, and selectively register the one or more unmap target map segments into the map update list according to the check result.

Abstract: A memory system includes a controller suitable for managing, first mapping information for mapping a number of first logical addresses among a logical addresses received from a host to a number of first physical addresses and second mapping information for mapping a number of second logical addresses among the logical addresses to a number of second physical addresses, the controller may compress the first mapping information of at least two first logical addresses, which are sequential, and at least two first physical addresses into first sequential mapping information, and may compress the second mapping information of at least two second logical addresses, which are sequential, and at least two second physical addresses into second sequential mapping information, the first physical addresses may be represented by a first number of bits, and the second physical addresses may be represented by a second number of bits.

Abstract: A multilayer ceramic electronic component includes a body including a dielectric layer, first and second internal electrodes, a stacked portion including first and second surfaces opposing each other in a stacking direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, and a coating layer disposed on the first to sixth surfaces of the stacked portion and having first and second connection portions; and first and second external electrodes connected to the first and second internal electrodes, respectively, and arranged on the third and fourth surfaces of the body, wherein the first and second internal electrodes are respectively connected to the first and second external electrodes through the first and second connection portions.

Abstract: A method for operating a data storage device which uses a nonvolatile memory device including a buffer memory block which temporarily stores data, as a storage medium, includes receiving an unmap request which requests that an unmap address be erased, from a host device; storing the unmap address and flag information indicating that the unmap address is unmapped, in a first empty page of the buffer memory block; and mapping the unmap address and flagging flag information indicating that the unmap address is unmapped, in a physical-to-logical (P2L) map corresponding to the first empty page of the buffer memory block.

Abstract: A data storage device may include a non-volatile memory device storing an address mapping table including a plurality of map segments and a controller including a random-access memory. The controller loads a compressed or non-compressed first map segment into the random-access memory based on meta-information of the first map segment in response to a read request received from a host device. The meta-information is stored in a map segment meta-information table stored in the random-access memory and the meta-information represents whether the map segments are compressible or not.

Abstract: The memory controller is provided to include: an operation controller configured to control memory devices to read first to third source pages and a source parity page in a source stripe and perform program operations on first to third target pages and a target parity page in a target stripe, a program data determiner configured to determine first to third program data to be programmed in the first to third target pages and to determine data read successfully from the first and second source pages as the first and second program data and determine recovery data as the third program data upon whether the read operation for the third source page has failed, and a parity calculator configured to generate calculation data by using the first and second program data, and generate the recovery data by using source parity data and the calculation data.