Patents by Inventor Byeong Gyu Park

Byeong Gyu Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200075260
    Abstract: A multilayer capacitor includes a body including a stacked structure of a plurality of dielectric layers and a plurality of internal electrodes, wherein, in the body, corners of cover portions are formed as curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and 0.8?Tg/Wg?1.2 in which Wg is a margin of the body in a width direction, and Tg is a margin of the body in a thickness direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: March 5, 2020
    Inventors: Yong Jin YUN, Byeong Gyu PARK, So Ra KANG, Jung Min PARK, Jea Yeol CHOI
  • Publication number: 20200075259
    Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and an external electrode. A cover portion of the body has curved corners, and a radius of curvature, R, of each of the curved corners and a thickness, T, of the body satisfy a condition of 10 ?m?R?T/3, and a width, W, and a thickness, T, of the body satisfy a condition of T/W<0.8.
    Type: Application
    Filed: July 30, 2019
    Publication date: March 5, 2020
    Inventors: Byeong Gyu Park, Yong Jin Yun, So Ra Kang, Jung Min Park, Jea Yeol Choi
  • Publication number: 20200065241
    Abstract: A data storage device includes a nonvolatile memory device including an address mapping table; a memory including a sequential map table in which sequential map entries for consecutive logical block addresses among logical block addresses are stored, the logical block addresses being received with write requests from a host device; and a processor configured to read one or more map segments, including logical block addresses of which mapping information is to be updated, from the address mapping table when a map update operation is triggered, store the read one or more map segments in the memory, sequentially change physical block addresses mapped to the respective logical block addresses to be updated, using a first sequential map entry including the logical block addresses to be updated which are stored in the sequential map table, and store the changed physical block addresses in the memory.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 27, 2020
    Inventors: Young Ick CHO, Byeong Gyu PARK, Sung Kwan HONG
  • Publication number: 20200042225
    Abstract: A data processing system includes a host configured to handle data in response to an input entered from an external, and a plurality of memory systems engaged with the host and configured to store or output the data in response to a request generated by the host. A first memory system among the plurality of memory systems accesses a specific location therein in response to a read command and an address delivered from the host. The first memory system outputs subject data read from the specific location to the host. The first memory system migrates the subject data to another memory system among the plurality of memory systems according to an operational state of the specific location.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 6, 2020
    Inventors: Ik-Sung OH, Byeong-Gyu PARK
  • Patent number: 10552333
    Abstract: An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Byeong Gyu Park
  • Publication number: 20200027661
    Abstract: A multilayer capacitor includes a body and external electrodes on external surfaces of the body. The body includes a plurality of internal electrodes alternately laminated with dielectric layers. The external electrodes are electrically connected to the internal electrodes. Edges of cover portions of the body are rounded. The rounded edges have a radius of curvature R and the body has a thickness T, such that R and T satisfy 10 ?m?R?T/4. Among the plurality of internal electrodes, an internal electrode in each of the cover portions has a width less than that of an internal electrode of the central portion.
    Type: Application
    Filed: December 13, 2018
    Publication date: January 23, 2020
    Inventors: Byeong Gyu PARK, Yong Jin YUN, So Ra KANG, Jae Yeol CHOI
  • Publication number: 20200019507
    Abstract: A controller includes a determination component suitable for determining whether target map data corresponding to a read request is compressible and a compression ratio for the target map data; a memory suitable for storing a meta table in which information on whether the target map data is compressible and the compression ratio for the target map data are contained, the memory comprising a map cache buffer including a retention area and a non-retention area; a compressor suitable for compressing the target map data at the determined compression ratio, when it is determined that the target map data is compressible; and a processor suitable for storing the compressed target map data in the retention area.
    Type: Application
    Filed: April 11, 2019
    Publication date: January 16, 2020
    Inventors: Young-Ick CHO, Byeong-Gyu PARK, Sung-Kwan HONG
  • Publication number: 20200019338
    Abstract: A controller may include: a memory suitable for storing map data and unmap data; a counter suitable for counting a number of the unmap data stored in the memory; a setter suitable for setting offset values to each of the unmap data when the number of the unmap data is equal to or greater than a predetermined threshold value; and a compressor suitable for compressing the unmap data to have a predetermined compression length based on the offset values.
    Type: Application
    Filed: April 16, 2019
    Publication date: January 16, 2020
    Inventors: Byeong-Gyu PARK, Young-Ick CHO, Seung-Gu JI
  • Patent number: 10534704
    Abstract: A controller includes a memory suitable for storing valid data of first data in a first data region and storing second data in a second data region, wherein the first data includes the valid data and dummy data; a translation unit suitable for performing a first translation operation of changing the first data to the valid data by eliminating the dummy data from the first data, performing a second translation operation of changing the valid data to the first data by adding the dummy data to the valid data, and exchanging the valid data with the memory; and a processor suitable for exchanging the first data with the translation unit, and exchanging the second data with the memory.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Byeong-Gyu Park, Kyu-Min Lee
  • Publication number: 20190391915
    Abstract: An operating method of a memory system includes receiving a read request for sequential target user data; determining whether compressed target map data corresponding to the read request are retrieved from a map cache region within a memory; loading the compressed target map data and compressed candidate map data from a memory device of the memory system, when the compressed target map data are not retrieved from the map cache region, the compressed candidate map data being selected from among compressed map data in a compressed map table, according to a rule; and storing the loaded compressed target map data and compressed candidate map data in the map cache region.
    Type: Application
    Filed: December 31, 2018
    Publication date: December 26, 2019
    Inventors: Se-Hyun KIM, Byeong-Gyu PARK
  • Publication number: 20190369918
    Abstract: An operating method of a memory system may include: allocating target map data to a target slot, among a plurality of slots within a compression engine; compressing the target map data to a set size in the target slot; switching the state of the target slot to a second state, when the compression is completed; generating an interrupt signal and providing the interrupt signal to a processor, when the state of the target slot is switched to the second state; providing a release command for the target slot to the compression engine in response to the interrupt signal; and switching the state of the target slot to the first state in response to the release command.
    Type: Application
    Filed: December 18, 2018
    Publication date: December 5, 2019
    Inventors: Young-Ick CHO, Sung-Kwan HONG, Byeong-Gyu PARK
  • Publication number: 20190361804
    Abstract: A memory system includes a controller suitable for managing, first mapping information for mapping a number of first logical addresses among a logical addresses received from a host to a number of first physical addresses and second mapping information for mapping a number of second logical addresses among the logical addresses to a number of second physical addresses, the controller may compress the first mapping information of at least two first logical addresses, which are sequential, and at least two first physical addresses into first sequential mapping information, and may compress the second mapping information of at least two second logical addresses, which are sequential, and at least two second physical addresses into second sequential mapping information, the first physical addresses may be represented by a first number of bits, and the second physical addresses may be represented by a second number of bits.
    Type: Application
    Filed: December 19, 2018
    Publication date: November 28, 2019
    Inventor: Byeong-Gyu PARK
  • Patent number: 10489084
    Abstract: A method of a read reclaim operation of a memory controller, the method comprising: updating, during each read operation for a read operation unit among one or more read operation units included in each of a plurality of memory blocks, a first index for a corresponding one among the plurality of memory blocks and a second index for the read operation unit; detecting a warming block, the first index of which is over a first threshold among the plurality of memory blocks; detecting a read-hot-spot, the updated second index of which is over a second threshold among the read operation units included in the warming block; and performing the read reclaim operation on the read-hot-spot.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Byeong-Gyu Park, Seung-Gu Ji
  • Publication number: 20190339868
    Abstract: A method for operating a memory system includes checking, by a memory device manager, an available capacity of a memory device in response to a write request transmitted from a host device; determining, by the memory device manager, a parallel access size based on the available capacity; comparing, by the memory device manager, a size of host data to be written in one or more nonvolatile memory devices in response to the write request, with the available capacity; receiving, by the memory device manager, host data of a first size in the memory device from the host device; and writing, by an access unit, the host data received in the memory device, to the nonvolatile memory devices by a unit of the parallel access size.
    Type: Application
    Filed: November 27, 2018
    Publication date: November 7, 2019
    Inventors: Seung Gu JI, Byeong Gyu PARK
  • Publication number: 20190303285
    Abstract: The memory controller includes an unmap controller configured to receive unmap information from a host, calculate operation times required to perform a plurality of respective unmap operations based on the unmap information, and output an unmap command for an unmap operation having a relatively short operation time among the plurality of unmap operations as a result of the calculation; a buffer memory configured to store a plurality of types of address mapping information; and a control processor configured to control the unmap controller and the buffer memory in response to a command received from the host.
    Type: Application
    Filed: October 3, 2018
    Publication date: October 3, 2019
    Inventors: Byeong Gyu PARK, Seung Gu JI
  • Publication number: 20190278716
    Abstract: In a memory controller for controlling an operation of a memory device, the memory controller includes a map table buffer, a compressed map buffer, and a processor. The map table buffer stores map data received from the memory device. The compressed map buffer stores compressed map data generated by compressing the map data. The processor controls operations of the map table buffer and the compressed map buffer.
    Type: Application
    Filed: October 11, 2018
    Publication date: September 12, 2019
    Inventors: Young Ick CHO, Byeong Gyu PARK, Sung Kwan HONG
  • Publication number: 20190258568
    Abstract: Provided herein may be a storage device and a method of operating the same. A method of operating a memory controller Included in a storage device for processing an unmap request may include receiving an unmap request for requesting deletion of address mapping information for an unmap address from a host, storing the unmap address and prestored unmap-pattern data in a random access memory (RAM), and outputting the unmap-pattern data to the host in response to a read request for the unmap address being inputted.
    Type: Application
    Filed: September 24, 2018
    Publication date: August 22, 2019
    Inventors: Byeong Gyu PARK, Seung Gu JI
  • Patent number: 10388387
    Abstract: A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages suitable for storing data; and a controller suitable for receiving a plurality of commands from a host, performing a plurality of command executions on the plurality of memory blocks in response to the plurality of commands, checking parameters of the plurality of memory blocks according to the plurality of command executions performed on the plurality of memory blocks, selecting first memory blocks among the plurality of memory blocks according to the parameters, and copying data stored in the first memory blocks to second memory blocks among the plurality of memory blocks.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Byeong-Gyu Park
  • Publication number: 20190251035
    Abstract: An operating method for a data storage device may include: reading data from a first memory region of a storage medium; storing the read data in a data buffer; and writing the data stored in the data buffer to a second memory region of the storage medium, based on a read count for the first memory region.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Seung Gu JI, Byeong Gyu PARK
  • Patent number: 10366776
    Abstract: A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable for detecting two or more bad super memory blocks each including at least one bad block among the super memory blocks, selecting at least one victim super memory block among the bad super memory blocks, and replacing the at least one bad block in each remaining bad super memory block with at least one normal block of the victim super memory block.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Ik-Sung Oh, Byeong-Gyu Park, Kyu-Min Lee